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Entry Level Asic Design Engineer Jobs in Texas (NOW HIRING)

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Entry Level Asic Design Engineer information

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$87.6K

$139.9K

$188.2K

How much do entry level asic design engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for entry level asic design engineer in Texas is $139,930.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,500.00 and $167,700.00 per year, depending on experience, location, and employer.

What is an entry level ASIC design engineer?

An Entry Level ASIC Design Engineer is responsible for assisting in the design, development, and testing of Application-Specific Integrated Circuits (ASICs). They work with senior engineers to define specifications, write hardware descriptions using languages like Verilog or VHDL, and perform simulations to validate designs. They may also collaborate with verification teams, support synthesis and timing analysis, and help troubleshoot design issues. This role requires a strong foundation in digital logic design, semiconductor fundamentals, and hardware design methodologies.

What are the typical daily responsibilities for an entry level ASIC design engineer?

As an Entry Level ASIC Design Engineer, your daily tasks often include writing and debugging code in hardware description languages, running simulations to verify functionality, and collaborating with senior engineers to implement and optimize chip designs. You may also assist with testbench development, participate in design reviews, and document your progress for project tracking. Expect to work closely with a multidisciplinary team—including verification, layout, and software engineers—to ensure the final product meets performance and reliability standards. This collaborative, fast-paced environment provides valuable hands-on experience and growth opportunities for engineers early in their careers.

What are the key skills and qualifications needed to thrive in the entry level ASIC design engineer position, and why are they important?

To thrive as an Entry Level ASIC Design Engineer, you need a solid understanding of digital logic design, hardware description languages (such as Verilog or VHDL), and a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Synopsys or Cadence and experience with simulation and verification environments are commonly expected. Strong problem-solving skills, effective communication, and the ability to work collaboratively make candidates stand out. These competencies enable precise design, successful project collaboration, and adaptation to the fast-paced, detail-oriented nature of ASIC development.

What are the most commonly searched types of Asic Design Engineer jobs in Texas?

The most popular types of Asic Design Engineer jobs in Texas are:

What are popular job titles related to Entry Level Asic Design Engineer jobs in Texas?

For Entry Level Asic Design Engineer jobs in Texas, the most frequently searched job titles are:

What job categories do people searching Entry Level Asic Design Engineer jobs in Texas look for?

The top searched job categories for Entry Level Asic Design Engineer jobs in Texas are:

What cities in Texas are hiring for Entry Level Asic Design Engineer jobs?

Cities in Texas with the most Entry Level Asic Design Engineer job openings:

Entry Level Asic Design Engineer jobs near you
Infographic showing various Entry Level Asic Design Engineer job openings in Texas as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $139,930 per year, or $67.3 per hour.

ASIC/SOC DFT Engineer (Silicon Engineering)

Austin, TX • On-site

SpaceX
Aerospace Product and Parts Manufacturing • 1 - 5K employees
Learn more about SpaceXexternal

$164K/yr

Full-time

Re-posted 8 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 152 frontline employees who took The Breakroom Quiz

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
  • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
  • Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
  • Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
  • Run and debug non-timing and SDF annotated gate level simulations
  • Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
  • Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 1+ years of professional experience working with ASICs
  • Experience in scan insertion or DFT setup

PREFERRED SKILLS AND EXPERIENCE:
  • Understanding of ASIC design flow, methodologies, physical design, and verification
  • Experience with high reliability design and implementations
  • Good scripting skills (csh/bash, Perl, Python etc.)
  • Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
  • Familiar with UPF (unified power format), formal verification, and DRC rule checking experience
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis
  • Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:
  • Must be willing to work extended hours and weekends as needed

ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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