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Entry Level Asic Design Engineer Jobs in Texas (NOW HIRING)

Meta

ASIC Engineer, Architecture

Austin, TX

$114K/yr

As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...

Qualcomm

Physical Design Engineer- senior

Austin, TX · On-site

$115K - $173K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Qualcomm

Physical Design Engineer- senior

Austin, TX · On-site

$99K - $135K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Meta

ASIC Engineer, Design

Austin, TX

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions,

Apple

Timing Design Engineer

Austin, TX

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...

Apple

Timing Design Engineer

Austin, TX · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...

Raytheon

FPGA ENGINEER II

Mckinney, TX

$114K - $157K/yr

We are currently seeking an FPGA Engineer II to join our team. This position is an onsite role ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

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All JobsAsic Design Engineer JobsEntry Level Asic Design Engineer JobsEntry Level Asic Design Engineer Jobs in Texas

Entry Level Asic Design Engineer information

See Texas salary details

$87.6K

$139.9K

$188.2K

How much do entry level asic design engineer jobs pay per year?

As of Aug 11, 2026, the average yearly pay for entry level asic design engineer in Texas is $139,930.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,500.00 and $167,700.00 per year, depending on experience, location, and employer.

What is an entry level ASIC design engineer?

An Entry Level ASIC Design Engineer is responsible for assisting in the design, development, and testing of Application-Specific Integrated Circuits (ASICs). They work with senior engineers to define specifications, write hardware descriptions using languages like Verilog or VHDL, and perform simulations to validate designs. They may also collaborate with verification teams, support synthesis and timing analysis, and help troubleshoot design issues. This role requires a strong foundation in digital logic design, semiconductor fundamentals, and hardware design methodologies.

What are the typical daily responsibilities for an entry level ASIC design engineer?

As an Entry Level ASIC Design Engineer, your daily tasks often include writing and debugging code in hardware description languages, running simulations to verify functionality, and collaborating with senior engineers to implement and optimize chip designs. You may also assist with testbench development, participate in design reviews, and document your progress for project tracking. Expect to work closely with a multidisciplinary team—including verification, layout, and software engineers—to ensure the final product meets performance and reliability standards. This collaborative, fast-paced environment provides valuable hands-on experience and growth opportunities for engineers early in their careers.

What are the key skills and qualifications needed to thrive in the entry level ASIC design engineer position, and why are they important?

To thrive as an Entry Level ASIC Design Engineer, you need a solid understanding of digital logic design, hardware description languages (such as Verilog or VHDL), and a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Synopsys or Cadence and experience with simulation and verification environments are commonly expected. Strong problem-solving skills, effective communication, and the ability to work collaboratively make candidates stand out. These competencies enable precise design, successful project collaboration, and adaptation to the fast-paced, detail-oriented nature of ASIC development.

What are the most commonly searched types of Asic Design Engineer jobs in Texas? The most popular types of Asic Design Engineer jobs in Texas are:
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Entry Level Asic Design Engineer jobs near you
Infographic showing various Entry Level Asic Design Engineer job openings in Texas as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $139,930 per year, or $67.3 per hour.

ASIC Engineer, Architecture

Meta

Austin, TX

$114K/yr

Full-time

Re-posted 5 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

136th of 242 rated software companies

Job description

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in architecture, performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish functional and performance modeling methodologies and long-term silicon roadmap strategy, as well as develop and analyze workloads, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.
ASIC Engineer, Architecture Responsibilities:
  • Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisions
  • Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments
  • Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration, performance analysis, and software development
  • Develop low-level workloads and kernels for machine learning training and inference applications
  • Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline
  • Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications
  • Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics
  • Lead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadership
  • Define long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investments
  • Mentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practices
  • Identify and resolve performance gaps between modeled and measured silicon behavior through structured root-cause analysis and model calibration

Minimum Qualifications:
  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 2+ years of experience in ASIC design, silicon engineering, or a related technical field
  • Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools
  • Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs
  • Experience with the performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon
  • Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems, including processors, memory subsystems, or high-speed interconnects
  • Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams
  • Experience with assembly programming languages, and with compiler technologies

Preferred Qualifications:
  • Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis
  • Experience writing and optimizing compute/collective kernels in CUDA or equivalent GPU programming frameworks
  • Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies
  • Experience with AI numerics, data types, math functions, and precision/accuracy analysis
  • Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization
  • Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs
  • Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$114,000/year to $172,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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