Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities. Attend and drive technical sessions with DRAM vendors ...
Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities. Attend and drive technical sessions with DRAM vendors ...
Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities. Attend and drive technical sessions with DRAM vendors ...
Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities. Attend and drive technical sessions with DRAM vendors ...
Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities. Attend and drive technical sessions with DRAM vendors ...
Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities. Attend and drive technical sessions with DRAM vendors ...
Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-generati...
Richardson, TX · On-site
As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked ...
Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-generati...
Richardson, TX · On-site
As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked ...
Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-generation
Richardson, TX · On-site
As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked ...
Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-generation
Richardson, TX · On-site
As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked ...
If you enjoy working across engineering, business, and executive teams to drive real impact, this ... Own revenue, margin, and share for enterprise DRAM and NAND across a major global OEM account * Act ...
If you enjoy working across engineering, business, and executive teams to drive real impact, this ... Own revenue, margin, and share for enterprise DRAM and NAND across a major global OEM account * Act ...
HBM Design Engineering Lead - MTS/SMTS/DMTS
$93K - $122K/yr
Using TSV (Through Silicon Via), we stack multiple DRAM chips on a high-speed memory controller ... You will influence future memory architectures while mentoring engineers and improving design ...
HBM Design Engineering Lead - MTS/SMTS/DMTS
$93K - $122K/yr
Using TSV (Through Silicon Via), we stack multiple DRAM chips on a high-speed memory controller ... You will influence future memory architectures while mentoring engineers and improving design ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via ... As a Senior Design Verification Engineer, you will collaborate closely with design, architecture ...
HBM Design Engineering Lead - MTS/SMTS/DMTS
Richardson, TX · On-site
$93K - $122K/yr
Apply deep knowledge of Dynamic Random-Access Memory (DRAM) operation, Joint Electron Device Engineering Council (JEDEC) specifications, memory subsystems, and high-speed interfaces to architect ...
HBM Design Engineering Lead - MTS/SMTS/DMTS
Richardson, TX · On-site
$93K - $122K/yr
Apply deep knowledge of Dynamic Random-Access Memory (DRAM) operation, Joint Electron Device Engineering Council (JEDEC) specifications, memory subsystems, and high-speed interfaces to architect ...
The Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role ...
The Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role ...
The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products.
The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products.
The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products.
The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products.
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... Develop DFT solutions for both base die and DRAM die, considering stacked-die and cube-level test ...
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... Develop DFT solutions for both base die and DRAM die, considering stacked-die and cube-level test ...
As a Principal Design Engineer, you will build the future of memory by architecting and delivering ... Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet ...
As a Principal Design Engineer, you will build the future of memory by architecting and delivering ... Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet ...
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... Develop DFT solutions for both base die and DRAM die, considering stackeddie and cubelevel test ...
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... Develop DFT solutions for both base die and DRAM die, considering stackeddie and cubelevel test ...
As a Principal Design Engineer, you will build the future of memory by architecting and delivering ... Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet ...
As a Principal Design Engineer, you will build the future of memory by architecting and delivering ... Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet ...
Principal HIG ESD and Latch-up Engineer- HBM - TPG
Richardson, TX · On-site
$175K - $297K/yr
This role plays a critical part in ensuring the reliability of Micron's most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design ...
Principal HIG ESD and Latch-up Engineer- HBM - TPG
Richardson, TX · On-site
$175K - $297K/yr
This role plays a critical part in ensuring the reliability of Micron's most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design ...
Dram Engineer information
What are DRAM Engineers?
What is the difference between Dram Engineer vs Memory Engineer?
| Aspect | Dram Engineer | Memory Engineer |
|---|---|---|
| Credentials | Bachelor's or higher in Electrical Engineering, Computer Engineering, or related fields; certifications like IEEE are common | Similar educational background; often holds certifications in memory design or semiconductor manufacturing |
| Work Environment | Design labs, semiconductor fabs, R&D centers | Design labs, semiconductor manufacturing facilities, R&D centers |
| Industry Usage | Memory chip companies, electronics manufacturers | Memory chip companies, electronics manufacturers |
| Job Focus | Design and optimize DRAM modules, ensure performance and reliability | Design and develop various types of memory, including DRAM, SRAM, Flash |
Both Dram Engineers and Memory Engineers work in similar environments and industries, often sharing educational backgrounds and certifications. While Dram Engineers focus specifically on DRAM technology, Memory Engineers may work on a broader range of memory types. The roles are closely related, with overlapping skills in semiconductor design and testing.
How does a DRAM Engineer typically collaborate with cross-functional teams during the memory development process?
What are the key skills and qualifications needed to thrive as a DRAM Engineer, and why are they important?

$166K - $296K/yr
Full-time
Medical, Dental, Retirement
Posted yesterday
Apple rating
8.0
Based on 675 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Description
The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.","responsibilities":"Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware, and Software.
Drive debug activities in post silicon environments, root-cause problems and steer the team to the best corrective action to move forward.
Plan and lead adoption of DRAM technologies, custom package development and qualification process with multi-functional teams.
Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities.
Attend and drive technical sessions with DRAM vendors on new DRAM technology development to track and follow-up issues/action items and drive vendors to meet spec and schedule requirements.
Work with DRAM GSM and silicon material management teams to plan and track distribution of new DRAM material across all systems in development.
Enable tight collaboration between Design for Test (DFT), Product/Test/QA engineering, SiVal and Systems teams during NPI to finalize SoC performance targets and screen requirements.
Drive internal program process to guarantee high quality silicon execution.
Preferred Qualifications
Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms.
Experience shipping high volume DRAMs / SoCs.
Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus.
Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management.
Excellent debugging skills. Proven track record to drive resolution of critical problems, while under pressure.
Ability to understand complex technical discussions and extract action plans.
Passionate to own/drive project development using well-defined metrics.
Thrives in dynamic schedule driven development environment.
Ability to succinctly summarize complex details for executive reporting.
Extraordinary leadership skills and ability to encourage team members with a dedication to see the bigger picture
Phenomenal leadership and social skills with a reciprocal approach.
Minimum Qualifications
BS + 10 years of relevant experience
Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $166,600 and $296,000, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976