... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ...
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ...
Methodology Engineer - Static RTL Verification
San Jose, CA · On-site
$101K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute tool-qualification regressions across complex AMD SoC designs, ensuring ...
Methodology Engineer - Static RTL Verification
San Jose, CA · On-site
$101K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute tool-qualification regressions across complex AMD SoC designs, ensuring ...
Hardware Design Engineer
San Jose, CA · On-site
$145K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in ...
Hardware Design Engineer
San Jose, CA · On-site
$145K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in ...
16218 - ASIC Digital Design, Sr Manager
Sunnyvale, CA · On-site
$204K - $306K/yr
... RTL design experience, with direct ownership of complex digital designs. • Deep expertise in USB digital design and architecture or similar protocols. • Strong understanding of ASIC design ...
16218 - ASIC Digital Design, Sr Manager
Sunnyvale, CA · On-site
$204K - $306K/yr
... RTL design experience, with direct ownership of complex digital designs. • Deep expertise in USB digital design and architecture or similar protocols. • Strong understanding of ASIC design ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Methodology Engineer - Static RTL Verification
$159K - $195K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute toolqualification regressions across complex AMD SoC designs, ensuring ...
Methodology Engineer - Static RTL Verification
$159K - $195K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute toolqualification regressions across complex AMD SoC designs, ensuring ...
Senior ASIC Design Verification Engineer
$170K - $250K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Quick apply
Senior ASIC Design Verification Engineer
$170K - $250K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Experience with RTL design using Verilog or SystemVerilog. Preferred qualifications: * Master ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
Experience with RTL design using Verilog or SystemVerilog. Preferred qualifications: * Master ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
Senior Design Verification Engineer
San Jose, CA · On-site
$142K - $206K/yr
Writing directed and random test cases, debugging failures, filing and closing bugs. * Review ... RTL design and testbench or test case is required. * Good communication skills. Job Type: Regular ...
Senior Design Verification Engineer
San Jose, CA · On-site
$142K - $206K/yr
Writing directed and random test cases, debugging failures, filing and closing bugs. * Review ... RTL design and testbench or test case is required. * Good communication skills. Job Type: Regular ...
Senior Design Verification Engineer
San Jose, CA · On-site
$142K - $206K/yr
Writing directed and random test cases, debugging failures, filing and closing bugs. * Review ... RTL design and testbench or test case is required. * Good communication skills. Job Type: Regular ...
Senior Design Verification Engineer
San Jose, CA · On-site
$142K - $206K/yr
Writing directed and random test cases, debugging failures, filing and closing bugs. * Review ... RTL design and testbench or test case is required. * Good communication skills. Job Type: Regular ...
Hardware Design Engineer
San Jose, CA · Hybrid
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in ...
Hardware Design Engineer
San Jose, CA · Hybrid
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in ...
Senior ASIC Design Engineer - Processor Subsystem
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... knowledge and direct experience on LEO satellite component development, design and in-orbit ...
Senior ASIC Design Engineer - Processor Subsystem
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... knowledge and direct experience on LEO satellite component development, design and in-orbit ...
FPGA Engineers
$144K - $199K/yr
Company Description Ajith Ajith at krgtech.com KRG Technologies, Inc., Direct : 661 367 8000 * 310 ... Creation of Emulation/Field Programmable Gate Array (FPGA) models from a RTL design using emulation ...
FPGA Engineers
$144K - $199K/yr
Company Description Ajith Ajith at krgtech.com KRG Technologies, Inc., Direct : 661 367 8000 * 310 ... Creation of Emulation/Field Programmable Gate Array (FPGA) models from a RTL design using emulation ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · Hybrid
$132K - $182K/yr
... reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful ... Fixed point design of signal processing blocks while working with systems engineers. * RTL coding ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · Hybrid
$132K - $182K/yr
... reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful ... Fixed point design of signal processing blocks while working with systems engineers. * RTL coding ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
... RTL design and micro-architecture * Proven experience with full-chip integration and timing closure * Led at least one full-chip tape-out within the last 3 years, with direct responsibility for ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
... RTL design and micro-architecture * Proven experience with full-chip integration and timing closure * Led at least one full-chip tape-out within the last 3 years, with direct responsibility for ...
Dir, CAD Eng • R&D
San Jose, CA · On-site
The Director of EDA Design Methodology & Infrastructure will lead the development and optimization ... RTL-to-GDSII, verification, physical design, timing closure, and sign-off. • Oversee compute ...
Dir, CAD Eng • R&D
San Jose, CA · On-site
The Director of EDA Design Methodology & Infrastructure will lead the development and optimization ... RTL-to-GDSII, verification, physical design, timing closure, and sign-off. • Oversee compute ...
Full-Time, Onsite (Hybrid) - Design Verification Engineer - Sunnyvale, CA / Redmond, WA / Austin, TX
Sunnyvale, CA · On-site
$159K - $194K/yr
... directed and random testcases . * Perform functional and code coverage analysis and work towards closure. * Debug simulation failures, analyze root causes, and work closely with RTL design teams.
Quick apply
Full-Time, Onsite (Hybrid) - Design Verification Engineer - Sunnyvale, CA / Redmond, WA / Austin, TX
Sunnyvale, CA · On-site
$159K - $194K/yr
... directed and random testcases . * Perform functional and code coverage analysis and work towards closure. * Debug simulation failures, analyze root causes, and work closely with RTL design teams.
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
Senior ASIC Design Engineer - Processor Subsystem
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... knowledge and direct experience on LEO satellite component development, design and in-orbit ...
Senior ASIC Design Engineer - Processor Subsystem
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... knowledge and direct experience on LEO satellite component development, design and in-orbit ...
Experience with RTL design using Verilog or SystemVerilog. Preferred qualifications: * Master ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
Experience with RTL design using Verilog or SystemVerilog. Preferred qualifications: * Master ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
Director Rtl Design information
Full-time
Posted 24 days ago
Advanced Micro Devices rating
8.4
Based on 7 frontline employees who took The Breakroom Quiz
22nd of 139 rated electronics manufacturers
Job description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
AMD is looking for an experienced technical leader to drive RTL design for future generations of AMD CPUs. In this role, you will manage a high-performing experienced team designing state-of-the-art microprocessors.
THE PERSON:
AMD is looking for an experienced, detail-oriented, and motivated engineering leader with strong people leadership, teamwork skills and strong technical expertise to manage design of x86 CPUs. You will have the opportunity to work on and learn some of the industry’s cutting edge micro-architectural designs while you create, drive, and execute AMD’s next generation of CPUs. Your contributions will impact products that span the global x86 market from server to desktop and laptop designs.
KEY RESPONSIBILITIES:
- Leading and coordinating a team of RTL design engineers across multiple design blocks
- Drive project design goals and dependencies with architects, DV, and physical design teams
- Drive implementation strategy to deliver quality, timely and cost-effective solutions
- Technical leadership to resolve complex design problems in a dynamic environment
- Participate in technical reviews of specifications, design, and test plans. Identify and address areas of concern to meet design quality objectives
PREFERRED SKILLS:
- Experience delivering multiple tape outs in a design leadership role
- Expertise in computer architecture, processor pipeline and memory hierarchy
- Experience designing Instruction Set Architecture of a complex microprocessor
- Scripting languages (e.g. Ruby, Python, or Perl)
ACADEMIC CREDENTIALS:
- BS or MS in EE, CE, or CS and relevant experience
LOCATION:
Santa Clara, California
This role is not eligible for visa sponsorship.
#LI-KR1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Qualifications:Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Education:UNAVAILABLEEmployment Type: FULL_TIMEAbout Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US