... direct-to-consumer products. You'll contribute to the innovation behind products loved by millions ... We research, design, and develop new technologies and hardware to make computing faster, seamless ...
... direct-to-consumer products. You'll contribute to the innovation behind products loved by millions ... We research, design, and develop new technologies and hardware to make computing faster, seamless ...
Design/Hardware Verification Engineer with Security Clearance
Carlsbad, CA · On-site
$139K - $170K/yr
As a Design Verification Engineer, you will work closely with our RTL development engineers, system ... directed, and system-level testbenches • Develop and maintain stimulus generators, drivers ...
Design/Hardware Verification Engineer with Security Clearance
Carlsbad, CA · On-site
$139K - $170K/yr
As a Design Verification Engineer, you will work closely with our RTL development engineers, system ... directed, and system-level testbenches • Develop and maintain stimulus generators, drivers ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · Hybrid
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · Hybrid
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Requisition ID: 77708 Description We are seeking an experienced and visionary Technical Director to ... Provide guidance on best practices for RTL design, synthesis, verification, and physical ...
Requisition ID: 77708 Description We are seeking an experienced and visionary Technical Director to ... Provide guidance on best practices for RTL design, synthesis, verification, and physical ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
Founding RTL Design Engineer (San Francisco)
San Francisco, CA · On-site
$180K - $250K/yr
Base pay range $180,000.00/yr - $250,000.00/yr Direct message the job poster from 80Twenty 80Twenty ... They say chip design never got its GPT moment as there is no training data: 99% of RTL data is ...
Founding RTL Design Engineer (San Francisco)
San Francisco, CA · On-site
$180K - $250K/yr
Base pay range $180,000.00/yr - $250,000.00/yr Direct message the job poster from 80Twenty 80Twenty ... They say chip design never got its GPT moment as there is no training data: 99% of RTL data is ...
Design Engineer III
Sunnyvale, CA · On-site
$161K - $197K/yr
Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem ... Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Design Engineer III
Sunnyvale, CA · On-site
$161K - $197K/yr
Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem ... Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Design Engineer III
$80 - $86/hr
Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem ... Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Design Engineer III
$80 - $86/hr
Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem ... Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Design Engineer III
Sunnyvale, CA · On-site
$159K - $194K/yr
Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain ... directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run ...
Quick apply
Design Engineer III
Sunnyvale, CA · On-site
$159K - $194K/yr
Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain ... directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run ...
FPGA Design Engineer
Los Angeles, CA · Hybrid
$132K - $182K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
FPGA Design Engineer
Los Angeles, CA · Hybrid
$132K - $182K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Design Verification Engineer/Analyst
San Jose, CA · On-site
$159K - $194K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Quick apply
Design Verification Engineer/Analyst
San Jose, CA · On-site
$159K - $194K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Design Verification Engineer III
Sunnyvale, CA · On-site
$159K - $194K/yr
Develop and execute verification plans for RTL blocks/IPs across the subsystem. * Build and ... write directed and constrained-random tests. * Drive functional coverage and assertion (SVA ...
Design Verification Engineer III
Sunnyvale, CA · On-site
$159K - $194K/yr
Develop and execute verification plans for RTL blocks/IPs across the subsystem. * Build and ... write directed and constrained-random tests. * Drive functional coverage and assertion (SVA ...
Design Verification Engineer - Viasat Government
Carlsbad, CA · On-site
$132.50 - $209.50/hr
Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate ... directed, and system-level testbenches * Develop and maintain stimulus generators, drivers ...
Design Verification Engineer - Viasat Government
Carlsbad, CA · On-site
$132.50 - $209.50/hr
Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate ... directed, and system-level testbenches * Develop and maintain stimulus generators, drivers ...
Design Verification Engineer - Viasat Government
Carlsbad, CA · On-site
$164K - $246K/yr
Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate ... directed, and system-level testbenches * Develop and maintain stimulus generators, drivers ...
Design Verification Engineer - Viasat Government
Carlsbad, CA · On-site
$164K - $246K/yr
Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate ... directed, and system-level testbenches * Develop and maintain stimulus generators, drivers ...
Methodology Engineer - Static RTL Verification
San Jose, CA · On-site
$101K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute tool-qualification regressions across complex AMD SoC designs, ensuring ...
Methodology Engineer - Static RTL Verification
San Jose, CA · On-site
$101K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute tool-qualification regressions across complex AMD SoC designs, ensuring ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Senior Design and Integration Engineer, Cloud TPU
Sunnyvale, CA · On-site
$163 - $237/hr
Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
Senior Design and Integration Engineer, Cloud TPU
Sunnyvale, CA · On-site
$163 - $237/hr
Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ...
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ...
TPU Hardware Design Engineer, Cloud
Sunnyvale, CA · On-site
$138 - $197/hr
Experience architecting RTL solutions and with ASIC synthesis flows. * Cross-functional engagement ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
TPU Hardware Design Engineer, Cloud
Sunnyvale, CA · On-site
$138 - $197/hr
Experience architecting RTL solutions and with ASIC synthesis flows. * Cross-functional engagement ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...
Methodology Engineer - Static RTL Verification
$159K - $195K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute toolqualification regressions across complex AMD SoC designs, ensuring ...
Methodology Engineer - Static RTL Verification
$159K - $195K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... Design and execute toolqualification regressions across complex AMD SoC designs, ensuring ...
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Google rating
8.8
Based on 103 frontline employees who took The Breakroom Quiz
49th of 246 rated software companies
Job description
info_outline
X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications:
Preferred qualifications:
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience with IP development or integration.
- Experience in ASIC development withVerilogor VHDL.
- Experience with a scripting language like Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
- Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
- Knowledge of high-performance and energy efficient design techniques.
- Knowledge of FPGA and emulation platforms.
- Knowledge of ASIC Verification or DFT.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
- Define microarchitecture for a subsystem.
- Integrate internal and/or external IP.
- Define microarchitecture of a small to medium size IP.
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Participate in test plan and coverage analysis of the sub-system and chip-level verification.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
About Google
Sourced by ZipRecruiter
Industry
Software development and technology, communication and media
Company size
10,000+ Employees
Headquarters location
Mountain View, CA, US