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Director Rtl Design Jobs in California (NOW HIRING)

Persimmons

RTL / Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend ... Direct contact of employees, officers, or board members regarding employment opportunities is ...

Persimmons

RTL / Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend ... Direct contact of employees, officers, or board members regarding employment opportunities is ...

Google

RTL Design Engineer, TPU Compute

Sunnyvale, CA · On-site

Work with design validation (DV) teams to create testplans to verify, and debug design RTL. * Work ... directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant ...

Credo, Inc

Director, ASIC Design

San Jose, CA

$210K - $240K/yr

About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...

Silvus Technologies

FPGA Design Engineer

Los Angeles, CA · Hybrid

$132K - $182K/yr

THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...

Credo, Inc

Director, ASIC Design

San Jose, CA · On-site

$210K - $240K/yr

About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...

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Senior Director Digital Design - 16907

Senior Director Digital Design - 16907

Synopsys

Sunnyvale, CA • On-site

$229K - $343K/yr

Full-time

Posted 13 days ago

Job description

General Information
Job Title
Senior Director Digital Design - 16907
Job ID
16907
City
Sunnyvale
State/Province
California
Date Posted
08-Apr-2026
Job Category
Engineering
Job Subcategory
ASIC Digital Design
Hire Type
Employee
Remote Eligible
No
Base Salary Range: $229000 - $343000
Descriptions & Requirements
Job Description and Requirements
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have built your career in digital design where execution determines silicon success. You understand the difference between RTL that synthesizes cleanly and code that creates downstream timing problems. You have closed timing on multi-GHz datapaths, resolved clock domain crossing issues, and made power versus performance tradeoffs that define successful products.
High-speed interconnect is your domain. You understand SerDes and die-to-die links, sub-nanosecond latency requirements, and reliable link training logic. You still review critical RTL because that is where decisions are made. When timing reports show violations, you identify root cause. At Synopsys, you will lead digital design for interconnect solutions enabling AI systems to scale.
What You'll Be Doing
  • Lead digital design for high-speed die-to-die interconnect ICs from microarchitecture through physical design handoff
  • Direct RTL development, logic synthesis, timing closure, and clock domain crossing verification
  • Oversee DFT implementation including scan insertion, ATPG, MBIST, and boundary scan
  • Manage verification strategy, testbench architecture, assertion-based verification, and coverage closure
  • Guide pre-silicon validation using emulation platforms for link training and error recovery testing
  • Conduct technical reviews of microarchitecture, RTL quality, synthesis QoR, and verification plans
The Impact You Will Have
  • You will establish RTL architecture and implementation methodology for interconnect IPs enabling next-generation AI systems
  • Your synthesis and timing strategies will determine whether designs meet frequency targets within power budgets
  • The verification infrastructure you develop will impact first-silicon success and reduce debug cycles
  • Your DFT architecture will influence test coverage, yield learning, and production test economics
  • Your technical decisions on clock architecture and datapath optimization will affect product competitiveness
What You'll Need
  • 15+ years digital design experience with multiple high-speed ASIC tapeouts, including 5+ years in technical leadership
  • Strong expertise in SystemVerilog RTL design including complex FSMs, pipelined datapaths, and clock domain crossing
  • Demonstrated experience with logic synthesis and timing closure on multi-GHz designs
  • Proven background in high-speed digital design for SerDes, PHY, or die-to-die interconnect
  • Comprehensive DFT experience including scan design, ATPG, MBIST, and boundary scan
  • Solid foundation in digital verification including UVM, assertions, and formal verification
Who You Are
  • You analyze timing reports and distinguish architectural issues from transient concerns
  • You evaluate verification plans for completeness, identifying gaps in corner case coverage
  • You assess RTL for synthesis implications, recognizing structures that create timing or area challenges
  • You make informed tradeoffs between latency, throughput, power, and area based on requirements
  • You have developed engineers in metastability handling, gray code crossing, and low-latency optimization
The Team You'll Be Part Of
You will lead the digital design organization within Silicon Engineering, focused on high-bandwidth, ultra-low-latency die-to-die links for AI compute and networking systems. The team covers RTL design, logic synthesis, timing closure, DFT, digital verification, emulation, and program execution. You will work with analog design on PHY interfaces, physical implementation on timing closure, and system architects on protocol and performance requirements.
#LI-SW1
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
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About Synopsys

Sourced by ZipRecruiter

Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software partner for creative companies developing the electronic products and software applications we rely on every single day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer building advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver exceptional, secure products for the era of connected everything. The company is headquartered in Mountain View, California, and has approximately 113 offices located throughout North America, South America, Europe, Japan, Asia and India. Since 1986, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems that are found in the electronics that people rely on every single day.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Mountain View, CA, US

Year founded

1986

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