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Design And Analysis Engineer Jobs in California (NOW HIRING)

Solidigm

Failure Analysis Engineer

Rancho Cordova, CA · On-site

$121K - $194K/yr

This is a golden opportunity for the right applicant to join us and help design, build, and lead ... This Senior Failure Analysis Engineer will debug Solid State Drive (SSD) failures discovered during ...

Solidigm

Failure Analysis Engineer

Rancho Cordova, CA

This is a golden opportunity for the right applicant to join us and help design, build, and lead ... This Senior Failure Analysis Engineer will debug Solid State Drive (SSD) failures discovered during ...

Oklo

Neutronics Analysis Engineer

Santa Clara, CA · On-site

The engineer will also support verification and validation activities and contribute to licensing ... Be aware of and familiar with fast reactor core design and analysis work being performed ...

Oklo

Shielding Analysis Engineer

Santa Clara, CA · On-site +1

Position Description The Shielding Analysis Engineer is responsible for defining, developing, and ... This role involves working closely with the broader design team to solicit and capture requirements ...

Oklo

Neutronics Analysis Engineer

Santa Clara, CA · On-site +1

The engineer will also support verification and validation activities and contribute to licensing ... Be aware of and familiar with fast reactor core design and analysis work being performed ...

Zipline

Failure Analysis Engineer

San Francisco, CA

We design, build, and operate the world's largest autonomous logistics system, delivering critical ... As a Failure Analysis Engineer, you will investigate failures from fielded systems, development ...

SolarEdge

Failure Analysis Engineer

Milpitas, CA · On-site

We are looking for a Failure Analysis Engineer who loves digging into tough hardware problems ... Translate findings into crisp, actionable reports that help design, reliability, and engineering ...

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Design And Analysis Engineer information

What is the difference between Design And Analysis Engineer vs Mechanical Engineer?

AspectDesign And Analysis EngineerMechanical Engineer
CredentialsBachelor's or Master's in Mechanical, Aerospace, or related fields; certifications like CAD or FEABachelor's or Master's in Mechanical Engineering; similar certifications
Work EnvironmentDesign labs, simulation centers, manufacturing settingsManufacturing plants, design offices, testing facilities
Industry UsageProduct design, simulation, structural analysisProduct development, manufacturing, systems integration

Design And Analysis Engineers focus on creating and testing product designs using simulations and analysis tools, while Mechanical Engineers often work across broader engineering tasks including manufacturing and systems integration. Both roles require similar credentials and often overlap in work environments, but their primary focus differs on design versus broader engineering functions.

What is a design and analysis engineer?

Design and Analysis Engineers are professionals who create, evaluate, and improve products or systems using engineering principles and specialized software. They focus on designing components or structures and then analyzing them to ensure they meet required specifications, safety standards, and performance criteria. Their work often involves computer-aided design (CAD), simulations, and collaborating with other engineers to refine and validate designs before production. They play a crucial role in industries like aerospace, automotive, civil, and manufacturing.

How does a design and analysis engineer typically collaborate with cross-functional teams during a project?

Design and Analysis Engineers often work closely with multidisciplinary teams, including product designers, manufacturing specialists, and quality assurance personnel. Throughout a project, they participate in design reviews, share analysis results, and incorporate feedback to refine product concepts. Effective communication and teamwork are essential, as their insights help ensure that designs are both innovative and manufacturable. Regular meetings and collaborative software tools are commonly used to facilitate this dynamic workflow.

What are the key skills and qualifications needed to thrive as a design and analysis engineer, and why are they important?

A Design and Analysis Engineer typically requires a strong background in engineering principles, CAD proficiency, and a relevant engineering degree such as mechanical, aerospace, or civil engineering. Familiarity with simulation tools like ANSYS, SolidWorks, or MATLAB and certifications in these platforms are highly valued. Critical thinking, problem-solving, and effective communication are essential soft skills for collaborating on complex projects and presenting technical findings. These skills ensure the engineer can develop innovative solutions, validate designs, and contribute effectively to cross-functional engineering teams.
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Infographic showing various Design And Analysis Engineer job openings in California as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

Physical Design Engineer/Static Timing Analysis Engineer

VKore Solutions LLC

San Diego, CA • On-site

$144K - $148K/yr

Other

Posted 18 days ago

Job description

Urgent position of Physical Design Engineer/Static Timing Analysis Engineer

Location – San Diego,CA(Onsite)
Duration- Long Term

We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon-ready timing signoff.

The ideal candidate has strong fundamentals in static timing analysis, hands-on experience with industry signoff tools, and a proven track record of closing timing on complex, high-frequency designs at advanced FinFET technology nodes.

 

Key Responsibilities

Timing constraints (SDC): Develop, review, validate, and maintain timing constraints — clock definitions, generated clocks, I/O delays, false paths, multicycle paths, and clock-domain-crossing (CDC) exceptions — and ensure constraint consistency and quality.

Timing signoff: Perform block-level and full-chip static timing analysis and signoff using Synopsys PrimeTime / PrimeTime SI (and/or Cadence Tempus) across a full multi-mode multi-corner (MMMC) setup.

Timing closure: Analyze and close setup, hold, recovery/removal, and transition/capacitance violations; generate and implement timing ECOs and coordinate fixes with the place-and-route team.

Signal integrity: Run crosstalk delay and noise (SI) analysis, identify and resolve SI-induced violations, and correlate with extraction and physical data.

Parasitic correlation: Set up and validate RC parasitic extraction and SPEF (StarRC / Quantus QRC), manage RC corners, and ensure extraction-vs-signoff correlation.

Variation-aware analysis: Apply OCV / AOCV / POCV (SOCV) derating methodologies and drive accurate margin-aware signoff.

Hierarchical timing: Build and validate timing abstracts / interface models (ETM / ILM), perform interface timing budgeting, and support top-level integration for hierarchical designs.

Low-power timing: Handle UPF-based multi-voltage / multi-power-domain designs, including level shifters, isolation cells, and power-aware timing checks.

Flow & automation: Automate and enhance timing analysis and ECO flows using TCL / Python / Perl; improve turnaround time and reporting.

Collaboration & signoff quality: Work with synthesis, P&R, CTS, DFT, and IR/EM teams; document methodology, present timing reviews, and provide silicon-ready signoff sign-off criteria and reports.

Required Skills & Experience (Must-Have)

Strong fundamentals in static timing analysis — setup/hold, recovery/removal, timing arcs, slack, path groups, clock latency, uncertainty, and derating concepts.

Hands-on experience with Synopsys PrimeTime / PrimeTime SI for block and/or full-chip timing signoff.

Proficiency in SDC constraint development, debug, and validation (clocks, I/O timing, exceptions, CDC).

Experience with MMMC (multi-mode multi-corner) analysis and closure.

Understanding of OCV / AOCV / POCV variation-aware timing methodologies.

Working knowledge of crosstalk / signal-integrity analysis and noise closure.

Familiarity with parasitic extraction and SPEF (StarRC / Quantus QRC) and RC corner concepts.

Solid understanding of the physical design flow — synthesis, place-and-route, and clock tree synthesis — and its interaction with timing.

Exposure to advanced technology nodes (16nm / 7nm / 5nm / 3nm FinFET).

Strong scripting skills in TCL (mandatory); Python or Perl for flow automation.

Good debugging skills, clear communication, and the ability to work in a cross-functional, delivery-driven team.

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