Experience with ASIC design methodologies for clock domain checks, reset checks and low power ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Experience with ASIC design methodologies for clock domain checks, reset checks and low power ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
ASIC Engineer
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
ASIC Engineer
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$184K - $324K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$184K - $324K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Quick apply
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
$168 - $311/hr
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
$168 - $311/hr
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
ASIC Design Engineer New Grad
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
ASIC Design Engineer New Grad
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
RTL Design Engineer
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
RTL Design Engineer
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Senior RTL Design Engineer, TPU
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design. * Experience with SystemVerilog/RTL coding. * Experience with ...
Senior RTL Design Engineer, TPU
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design. * Experience with SystemVerilog/RTL coding. * Experience with ...
RTL Design Engineer
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
RTL Design Engineer
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Sr. RTL Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
Sr. RTL Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
ML ASIC Design Engineer
Mountain View, CA · On-site
$175K - $215K/yr
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
ML ASIC Design Engineer
Mountain View, CA · On-site
$175K - $215K/yr
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
Contractual Asic Rtl Design Engineer information
See Milpitas, CA salary details
$109.5K - $121K
16% of jobs
$121K - $132.4K
3% of jobs
$132.4K - $143.9K
4% of jobs
$147.2K is the 25th percentile. Wages below this are outliers.
$143.9K - $155.3K
6% of jobs
The median wage is $162.5K / yr.
$155.3K - $166.8K
33% of jobs
$166.8K - $178.2K
3% of jobs
$178.2K - $189.6K
2% of jobs
$197.2K is the 75th percentile. Wages above this are outliers.
$189.6K - $201.1K
12% of jobs
$201.1K - $212.5K
5% of jobs
$212.5K - $224K
4% of jobs
$224K - $235.4K
12% of jobs
$109.5K
$175K
$235.4K
How much do contractual asic rtl design engineer jobs pay per year?
As of Aug 23, 2026, the average yearly pay for contractual asic rtl design engineer in Milpitas, CA is $175,034.00, according to ZipRecruiter salary data. Most workers in this role earn between $153,200.00 and $209,800.00 per year, depending on experience, location, and employer.
What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Milpitas, CA?
The most popular types of Asic Rtl Design Engineer jobs in Milpitas, CA are:
What job categories do people searching Contractual Asic Rtl Design Engineer jobs in Milpitas, CA look for?
The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Milpitas, CA are:
What cities near Milpitas, CA are hiring for Contractual Asic Rtl Design Engineer jobs?
Cities near Milpitas, CA with the most Contractual Asic Rtl Design Engineer job openings:
Google rating
8.8
Based on 103 frontline employees who took The Breakroom Quiz
49th of 246 rated software companies
Job description
info_outline
X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications:
Preferred qualifications:
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience with IP development or integration.
- Experience in ASIC development withVerilogor VHDL.
- Experience with a scripting language like Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
- Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
- Knowledge of high-performance and energy efficient design techniques.
- Knowledge of FPGA and emulation platforms.
- Knowledge of ASIC Verification or DFT.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
- Define microarchitecture for a subsystem.
- Integrate internal and/or external IP.
- Define microarchitecture of a small to medium size IP.
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Participate in test plan and coverage analysis of the sub-system and chip-level verification.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
About Google
Sourced by ZipRecruiter
Industry
Software development and technology, communication and media
Company size
10,000+ Employees
Headquarters location
Mountain View, CA, US