RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
ASIC Physical Design Engineer / RTL Synthesis Engineer
San Jose, CA ยท On-site
$159K - $164K/yr
Hiring: Senior ASIC RTL-to-Physical Design (RTL2PD) / RTL Synthesis Engineer Location: San Jose, CA(onsite) Experience: 8 to 12 years What will Be Doing: * RTL Synthesis, Constraint writing ...
ASIC Physical Design Engineer / RTL Synthesis Engineer
San Jose, CA ยท On-site
$159K - $164K/yr
Hiring: Senior ASIC RTL-to-Physical Design (RTL2PD) / RTL Synthesis Engineer Location: San Jose, CA(onsite) Experience: 8 to 12 years What will Be Doing: * RTL Synthesis, Constraint writing ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
Senior ASIC (Front-End) Design Engineer
San Jose, CA ยท Hybrid
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
Senior ASIC (Front-End) Design Engineer
San Jose, CA ยท Hybrid
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
ASIC/RTL Design Engineer 2
San Jose, CA ยท On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
Quick apply
ASIC/RTL Design Engineer 2
San Jose, CA ยท On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
Physical Design Engineer - Synthesis & Floorplanning
Sunnyvale, CA ยท On-site
$161K - $166K/yr
Prodapt's ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification ... We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering ...
Physical Design Engineer - Synthesis & Floorplanning
Sunnyvale, CA ยท On-site
$161K - $166K/yr
Prodapt's ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification ... We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Integration RTL Design Engineer
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
Integration RTL Design Engineer
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Rtl Design Engineer - 2202600
Cupertino, CA ยท On-site
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
Rtl Design Engineer - 2202600
Cupertino, CA ยท On-site
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Senior Manager, ASIC Design Engineering
San Jose, CA ยท On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Senior Manager, ASIC Design Engineering
San Jose, CA ยท On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Quick apply
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Freelance Asic Rtl Design Engineer information
See Milpitas, CA salary details
$27.41 is the 25th percentile. Wages below this are outliers.
$17.37 - $29.80
31% of jobs
The median wage is $37.46 / hr.
$29.80 - $42.22
31% of jobs
$42.22 - $54.65
4% of jobs
$65.53 is the 75th percentile. Wages above this are outliers.
$54.65 - $67.08
10% of jobs
$67.08 - $79.51
9% of jobs
$79.51 - $91.94
5% of jobs
$91.94 - $104.36
0% of jobs
$104.36 - $116.79
8% of jobs
$116.79 - $129.22
0% of jobs
$129.22 - $141.65
0% of jobs
$141.65 - $154.08
1% of jobs
$17
$55
$154
How much do freelance asic rtl design engineer jobs pay per hour?
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Re-posted 4 days ago
Job description
Saratoga, CA
Full-Time
Join an innovative hardware company building next-generation Networking ASICs that power large-scale AI training and inference.
We are seeking experienced RTL Engineers to architect and implement high-performance networking chips focused on low latency, QoS, and scalability.
Responsibilities-
Design packet buffering, queuing, and scheduling microarchitecture
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Implement high-speed networking ASIC RTL (SystemVerilog/Verilog)
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Optimize pipelined architectures for performance and latency
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Support Ethernet, IP protocols, and high-speed interconnects (e.g., UCIe)
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Collaborate with verification teams for testing and validation
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BE/ME with 8โ15 years of ASIC RTL design experience
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Strong expertise in SystemVerilog & Verilog
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Experience with scheduling, arbitration & QoS mechanisms
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Solid understanding of ASIC design flow (simulation, synthesis, timing)
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Background in Ethernet and IP networking protocols
If youโre passionate about building high-speed networking silicon for AI infrastructure, apply today.