ASIC Engineer
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$184K - $324K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$184K - $324K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Santa Clara, CA · On-site
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Santa Clara, CA · On-site
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Quick apply
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Sunnyvale, CA · On-site
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation ...
Sunnyvale, CA · On-site
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation ...
Santa Clara, CA · On-site
$168 - $311/hr
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Santa Clara, CA · On-site
$168 - $311/hr
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design. * Experience with SystemVerilog/RTL coding. * Experience with ...
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design. * Experience with SystemVerilog/RTL coding. * Experience with ...
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Palo Alto, CA · On-site
$175K - $280K/yr
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
Palo Alto, CA · On-site
$175K - $280K/yr
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
Mountain View, CA · On-site
$175K - $215K/yr
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
Mountain View, CA · On-site
$175K - $215K/yr
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design ... You are expected to come up with micro-architecture, implement in RTL, and deliver a fully verified ...
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design ... You are expected to come up with micro-architecture, implement in RTL, and deliver a fully verified ...
$27.41 is the 25th percentile. Wages below this are outliers.
$17.37 - $29.80
31% of jobs
The median wage is $37.46 / hr.
$29.80 - $42.22
31% of jobs
$42.22 - $54.65
4% of jobs
$65.53 is the 75th percentile. Wages above this are outliers.
$54.65 - $67.08
10% of jobs
$67.08 - $79.51
9% of jobs
$79.51 - $91.94
5% of jobs
$91.94 - $104.36
0% of jobs
$104.36 - $116.79
8% of jobs
$116.79 - $129.22
0% of jobs
$129.22 - $141.65
0% of jobs
$141.65 - $154.08
1% of jobs
$17
$55
$154
The most popular types of Asic Rtl Design Engineer jobs in Milpitas, CA are:
For Freelance Asic Rtl Design Engineer jobs in Milpitas, CA, the most frequently searched job titles are:
The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Milpitas, CA are:
Cities near Milpitas, CA with the most Freelance Asic Rtl Design Engineer job openings:
Ideavat provides I.T staffing solutions, enabling companies & jobseekers engage successfully.
With over 20 man years of contingent staffing experience, the management & execution team is committed to provide customized staffing solutions to employers/hiring managers, helping them identify key talents. Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data/Hadoop developers & architects...& more) remains our primary focus!
Job Title: ASIC Engineer
Location: San Jose, CA
Duration: 6 Months
Minimum Required Skills:
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)
Description:
Should have 2-5 years of experience in FPGA/ASIC Development
Build RTL designs of digital circuits using VHDL and System Verilog
Perform frontend design development and integration of large ASIC designs
Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.
Write design documents including high level interface descriptions and design descriptions.
Write function test cases and test benches to verify functionality of designs
Team work and proactive sharing of knowledge
Comfortable working in a fast paced environment.
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)
All your information will be kept confidential according to EEO guidelines.
Sourced by ZipRecruiter
Josbridge Institute is your one-stop destination for your Data, Cloud and Analytics learning needs, powered by Microsoft AI & Cloud platform. We offer a wide range of courses and programs, from foundational to advanced focusing on Data Analysis, Cloud Engg, AI-ML required for Microsoft certification. Our courses are designed to equip you with the practical skills and knowledge required for success in the field of cloud computing, AI and Data Analytics. With our experienced faculty, applied learning and comprehensive curriculum, we are committed to helping you achieve your career goals. Students seeking Internship (CPT & OPT) may apply.
Business schools and computer and management training
11 - 50 Employees
Campbell, CA, US
2022