Overview At Cognichip, we're not just building AI--we're redefining what's possible at the nexus of ... Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design ...
Overview At Cognichip, we're not just building AI--we're redefining what's possible at the nexus of ... Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250 - $280/hr
Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Hands-on RTL Development * Write, review, and debug production-quality RTL in Verilog/SystemVerilog
ASIC Chip Design Lead
Saratoga, CA · On-site
$250 - $280/hr
Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Hands-on RTL Development * Write, review, and debug production-quality RTL in Verilog/SystemVerilog
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$100 - $150/hr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$100 - $150/hr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$150 - $210/hr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$150 - $210/hr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
Lead RTL Design Engineer
Sunnyvale, CA · On-site
$175 - $275/hr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
Lead RTL Design Engineer
Sunnyvale, CA · On-site
$175 - $275/hr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
Quick apply
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
Lead RTL Design Engineer
Sunnyvale, CA · On-site
$175K - $275K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
Lead RTL Design Engineer
Sunnyvale, CA · On-site
$175K - $275K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
Microarchitect / RTL Design - On-Chip Interconnect & High-Speed Fabric Design
Palo Alto, CA · On-site
$210 - $360/hr
We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ... Own the on-chip fabric RTL end-to-end : from NoC topology and router microarchitecture through code ...
Microarchitect / RTL Design - On-Chip Interconnect & High-Speed Fabric Design
Palo Alto, CA · On-site
$210 - $360/hr
We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ... Own the on-chip fabric RTL end-to-end : from NoC topology and router microarchitecture through code ...
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...
Our primary focus is AI acceleration. You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as ...
Our primary focus is AI acceleration. You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as ...
Senior RTL Design Engineer, TPU
Sunnyvale, CA · On-site
Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...
Senior RTL Design Engineer, TPU
Sunnyvale, CA · On-site
Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...
RTL generation, Design and Formal verification, PPA prediction and optimization. * Hands-on ... Wire coding agents and agentic AI into EDA and validation flows - simulation, regressions, waveform ...
RTL generation, Design and Formal verification, PPA prediction and optimization. * Hands-on ... Wire coding agents and agentic AI into EDA and validation flows - simulation, regressions, waveform ...
Physical Design Engineer
Sunnyvale, CA · On-site
$230 - $280/hr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D ...
Physical Design Engineer
Sunnyvale, CA · On-site
$230 - $280/hr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D ...
RTL generation, Design and Formal verification, PPA prediction and optimization. Hands-on ... Wire coding agents and agentic AI into EDA and validation flows - simulation, regressions, waveform ...
RTL generation, Design and Formal verification, PPA prediction and optimization. Hands-on ... Wire coding agents and agentic AI into EDA and validation flows - simulation, regressions, waveform ...
RTL generation, Design and Formal verification, PPA prediction and optimization. * Hands-on ... Wire coding agents and agentic AI into EDA and validation flows - simulation, regressions, waveform ...
RTL generation, Design and Formal verification, PPA prediction and optimization. * Hands-on ... Wire coding agents and agentic AI into EDA and validation flows - simulation, regressions, waveform ...
Microarchitect / RTL Design - Interconnect & Fabric
Palo Alto, CA · On-site
$210 - $320/hr
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on ... Own the on-chip fabric RTL end-to-end : from NoC topology and router microarchitecture through code ...
Microarchitect / RTL Design - Interconnect & Fabric
Palo Alto, CA · On-site
$210 - $320/hr
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on ... Own the on-chip fabric RTL end-to-end : from NoC topology and router microarchitecture through code ...
Ai Chip Design Rtl information
See Milpitas, CA salary details
$93.8K - $104.6K
0% of jobs
$104.6K - $115.4K
0% of jobs
$115.4K - $126.2K
1% of jobs
$126.2K - $137K
0% of jobs
$137K - $147.8K
0% of jobs
$152.3K is the 25th percentile. Wages below this are outliers.
$147.8K - $158.6K
57% of jobs
$163.3K is the 75th percentile. Wages above this are outliers.
$158.6K - $169.5K
38% of jobs
$169.5K - $180.3K
0% of jobs
$180.3K - $191.1K
1% of jobs
$191.1K - $201.9K
1% of jobs
$201.9K - $212.7K
1% of jobs
$93.8K
$162.4K
$212.7K
How much do ai chip design rtl jobs pay per year?
What is an AI Chip Design RTL engineer?
What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?
What are common challenges faced by AI Chip Design RTL engineers during the verification process?
What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?
| Aspect | Ai Chip Design Rtl | Ai Chip Verification Engineer |
|---|---|---|
| Primary Focus | Developing and implementing Register Transfer Level (RTL) code for AI chips | Verifying and validating RTL designs to ensure functionality |
| Skills Required | HDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledge | Simulation, testbench creation, debugging, scripting skills |
| Work Environment | Design teams, hardware development labs, EDA tools | Verification teams, simulation environments, test setups |
| Certifications | Hardware design certifications, FPGA/ASIC training | Verification methodologies, UVM, SystemVerilog certifications |
While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.
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Full-time
Re-posted 8 days ago
Job description
At Cognichip, we’re not just building AI—we’re redefining what’s possible at the nexus of silicon design and machine learning. As a Staff Chip Design Engineer on our team, you’ll tackle real-world scientific and coding challenges—defining the processes for dataset collection, curation, and enhancement. You’ll fuse knowledge of chip design and ML into end-to-end silicon design flows. If you thrive on pushing the envelope of research and translating cutting-edge ideas into production-grade systems, this is your stage.
What you\'ll do- Serve as the domain experts, embedding chip design experience into a team creating AI chip design assistants
- Bridge research and production. Collaborate closely with ML and SW teams to integrate experimental models into scalable pipelines.
- Define data-processing pipelines, training orchestration, and evaluation frameworks to accelerate iteration on large-scale experiments.
- Analyze and iterate. Dive deep into large datasets—experimental logs, simulation outputs, and user interaction traces—to diagnose model behavior, surface failure modes, and drive evidence-based improvements.
- Publish and present. Document findings in technical reports, contribute to open-source projects, and present work internally (and externally, when appropriate) to help shape the broader AI research community.
- Masters in Computer Science, Electrical Engineering, or a closely related field
- 10-15 years of experience in RTL design, or a combination of design and verification
- Proficiency in SystemVerilog and Python languages
- Excellent written and verbal communication skills, esp to convey chip design knowledge to scientists/engineers in other fields
- Comfortable working in a dynamic, research-heavy startup environment
- Demonstrated coursework or project experience in machine learning and/or deep learning
- Personal projects showcasing innovation, creativity, and continuous learning
- Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5, etc)
- Knowledge of open-source tools and contribution practices (Verilator, CocoTB, Yosys, OpenSTA, etc)
- Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design, etc)
- Experience with FPGA development (Vivado, Vitis, Quartus, etc), front end, IP integration, and/or back end
We’re a fast-moving AI startup with a collaborative, high-trust culture. You’ll work with top-tier engineers, scientists, and builders—solving hard problems that sit at the intersection of cloud computing, AI, and chip design. We value technical excellence, ownership, and the freedom to experiment. If you’re excited to build the future of engineering, you’ll feel right at home.
LogisticsThis position is available in Silicon Valley’s Redwood Shores, CA. We have a hybrid schedule with four days in office, one day remote. Cognichip accepts applications that need H1B transfer.
How to applyDon’t meet every single requirement? Feel over-qualified? That’s okay—if you\'re excited about our mission, we’d still love to hear from you. We are growing fast and need a world class team of various experience levels.