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Ai Chip Design Rtl Jobs in Milpitas, CA (NOW HIRING)

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...

ASIC Chip Design Lead

Saratoga, CA · On-site

$250 - $280/hr

Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Hands-on RTL Development * Write, review, and debug production-quality RTL in Verilog/SystemVerilog

We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Lead RTL Design Engineer

Sunnyvale, CA · On-site

$175K - $275K/yr

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...

Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...

Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...

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Ai Chip Design Rtl information

See Milpitas, CA salary details

$93.8K

$162.4K

$212.7K

How much do ai chip design rtl jobs pay per year?

As of Sep 5, 2026, the average yearly pay for ai chip design rtl in Milpitas, CA is $162,415.00, according to ZipRecruiter salary data. Most workers in this role earn between $158,500.00 and $158,500.00 per year, depending on experience, location, and employer.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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Infographic showing various Ai Chip Design Rtl job openings in Milpitas, CA as of August 2026, with employment types broken down into 81% Full Time, 13% Part Time, 2% Temporary, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $162,415 per year, or $78.1 per hour.

Staff Chip Design Engineer (Redwood City)

Cognichip

Redwood City, CA • On-site

Full-time

Re-posted 8 days ago


Job description

Overview

At Cognichip, we’re not just building AI—we’re redefining what’s possible at the nexus of silicon design and machine learning. As a Staff Chip Design Engineer on our team, you’ll tackle real-world scientific and coding challenges—defining the processes for dataset collection, curation, and enhancement. You’ll fuse knowledge of chip design and ML into end-to-end silicon design flows. If you thrive on pushing the envelope of research and translating cutting-edge ideas into production-grade systems, this is your stage.

What you\'ll do
  • Serve as the domain experts, embedding chip design experience into a team creating AI chip design assistants
  • Bridge research and production. Collaborate closely with ML and SW teams to integrate experimental models into scalable pipelines.
  • Define data-processing pipelines, training orchestration, and evaluation frameworks to accelerate iteration on large-scale experiments.
  • Analyze and iterate. Dive deep into large datasets—experimental logs, simulation outputs, and user interaction traces—to diagnose model behavior, surface failure modes, and drive evidence-based improvements.
  • Publish and present. Document findings in technical reports, contribute to open-source projects, and present work internally (and externally, when appropriate) to help shape the broader AI research community.
What You Bring
  • Masters in Computer Science, Electrical Engineering, or a closely related field
  • 10-15 years of experience in RTL design, or a combination of design and verification
  • Proficiency in SystemVerilog and Python languages
  • Excellent written and verbal communication skills, esp to convey chip design knowledge to scientists/engineers in other fields
  • Comfortable working in a dynamic, research-heavy startup environment
  • Demonstrated coursework or project experience in machine learning and/or deep learning
Bonus Points
  • Personal projects showcasing innovation, creativity, and continuous learning
  • Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5, etc)
  • Knowledge of open-source tools and contribution practices (Verilator, CocoTB, Yosys, OpenSTA, etc)
  • Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design, etc)
  • Experience with FPGA development (Vivado, Vitis, Quartus, etc), front end, IP integration, and/or back end
What it's like here

We’re a fast-moving AI startup with a collaborative, high-trust culture. You’ll work with top-tier engineers, scientists, and builders—solving hard problems that sit at the intersection of cloud computing, AI, and chip design. We value technical excellence, ownership, and the freedom to experiment. If you’re excited to build the future of engineering, you’ll feel right at home.

Logistics

This position is available in Silicon Valley’s Redwood Shores, CA. We have a hybrid schedule with four days in office, one day remote. Cognichip accepts applications that need H1B transfer.

How to apply

Don’t meet every single requirement? Feel over-qualified? That’s okay—if you\'re excited about our mission, we’d still love to hear from you. We are growing fast and need a world class team of various experience levels.

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