Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services ...
Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services ...
Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services ...
Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services ...
Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services ...
Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services ...
... of compact device models and characterize new technologies. This individual will perform characterization of electrical devices and develop models to closely replicate their behavior, for use in ...
... of compact device models and characterize new technologies. This individual will perform characterization of electrical devices and develop models to closely replicate their behavior, for use in ...
... of compact device models and characterize new technologies. This individual will perform characterization of electrical devices and develop models to closely replicate their behavior, for use in ...
... of compact device models and characterize new technologies. This individual will perform characterization of electrical devices and develop models to closely replicate their behavior, for use in ...
Device Modeling Senior Staff Engineer
$109K - $149K/yr
This SkyWater Device Modeling Senior Staff Engineer will primarily lead device characterization, perform compact model extraction, and contribute to device design for advanced CMOS-based technologies ...
Device Modeling Senior Staff Engineer
$109K - $149K/yr
This SkyWater Device Modeling Senior Staff Engineer will primarily lead device characterization, perform compact model extraction, and contribute to device design for advanced CMOS-based technologies ...
Device Modeling Senior Staff Engineer
Bloomington, MN · On-site
$114K - $171K/yr
This SkyWater Device Modeling Senior Staff Engineer will primarily lead device characterization, perform compact model extraction, and contribute to device design for advanced CMOS-based technologies ...
Device Modeling Senior Staff Engineer
Bloomington, MN · On-site
$114K - $171K/yr
This SkyWater Device Modeling Senior Staff Engineer will primarily lead device characterization, perform compact model extraction, and contribute to device design for advanced CMOS-based technologies ...
Device Modeling Senior Staff Engineer
Bloomington, MN · On-site
$114K - $171K/yr
This SkyWater Device Modeling Senior Staff Engineer will primarily lead device characterization, perform compact model extraction, and contribute to device design for advanced CMOS-based technologies ...
Device Modeling Senior Staff Engineer
Bloomington, MN · On-site
$114K - $171K/yr
This SkyWater Device Modeling Senior Staff Engineer will primarily lead device characterization, perform compact model extraction, and contribute to device design for advanced CMOS-based technologies ...
Quantum Cryo CMOS Design Enablement
$98K - $176K/yr
Contribute to development of cryogenic CMOS PDKs, including compact models, parameter extraction, and validation across temperature regimes. * Support device modeling efforts by correlating silicon ...
Quantum Cryo CMOS Design Enablement
$98K - $176K/yr
Contribute to development of cryogenic CMOS PDKs, including compact models, parameter extraction, and validation across temperature regimes. * Support device modeling efforts by correlating silicon ...
Quantum Cryo CMOS Design Enablement
New York, NY · On-site
$98K - $176K/yr
Contribute to development of cryogenic CMOS PDKs, including compact models, parameter extraction, and validation across temperature regimes. * Support device modeling efforts by correlating silicon ...
Quantum Cryo CMOS Design Enablement
New York, NY · On-site
$98K - $176K/yr
Contribute to development of cryogenic CMOS PDKs, including compact models, parameter extraction, and validation across temperature regimes. * Support device modeling efforts by correlating silicon ...
Strong foundational knowledge of semiconductor device physics, especially as it relates to compact modeling across various device types. * Proven hands-on experience performing deep-submicron CMOS ...
Strong foundational knowledge of semiconductor device physics, especially as it relates to compact modeling across various device types. * Proven hands-on experience performing deep-submicron CMOS ...
2026 PhD Residency - Non-Linear Physical Dynamics & Device Characterization (Future of Compute)
Mountain View, CA · On-site
$100K - $147K/yr
Develop compact device behavioral models (e.g., Verilog-A, analytical Python equations) derived directly from physical measurements to update our circuit and system-level simulators. This project ...
2026 PhD Residency - Non-Linear Physical Dynamics & Device Characterization (Future of Compute)
Mountain View, CA · On-site
$100K - $147K/yr
Develop compact device behavioral models (e.g., Verilog-A, analytical Python equations) derived directly from physical measurements to update our circuit and system-level simulators. This project ...
Quantum Cryo CMOS Design Enablement
New York, NY · On-site
$143K - $247K/yr
Build, lead, and develop a high-performance team spanning device modeling, test, characterization, and design enablement engineering. * Drive development of cryogenic CMOS PDKs, including compact ...
Quantum Cryo CMOS Design Enablement
New York, NY · On-site
$143K - $247K/yr
Build, lead, and develop a high-performance team spanning device modeling, test, characterization, and design enablement engineering. * Drive development of cryogenic CMOS PDKs, including compact ...
Quantum Cryo CMOS Design Enablement
Malta, NY · On-site
$143K - $247K/yr
Build, lead, and develop a high-performance team spanning device modeling, test, characterization, and design enablement engineering. * Drive development of cryogenic CMOS PDKs, including compact ...
Quantum Cryo CMOS Design Enablement
Malta, NY · On-site
$143K - $247K/yr
Build, lead, and develop a high-performance team spanning device modeling, test, characterization, and design enablement engineering. * Drive development of cryogenic CMOS PDKs, including compact ...
Quantum PDK Engineer
Essex Junction, VT · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
Essex Junction, VT · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
Essex Junction, VT · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
Essex Junction, VT · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
Malta, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
Malta, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
New York, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
New York, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
New York, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
New York, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
Malta, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Quantum PDK Engineer
Malta, NY · On-site
$98K - $176K/yr
The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes ...
Compact Device Modeling information
What are the key skills and qualifications needed to thrive as a Compact Device Modeling Engineer, and why are they important?
What types of teams or departments does a Compact Device Modeling engineer typically collaborate with?
What is compact device modeling?
What is the difference between Compact Device Modeling vs Semiconductor Device Engineer?
| Aspect | Compact Device Modeling | Semiconductor Device Engineer |
|---|---|---|
| Credentials | Typically requires engineering degree, specialized modeling certifications | Requires engineering degree, often with additional certifications in device physics |
| Work Environment | Research labs, simulation centers, R&D departments | Design labs, manufacturing facilities, R&D teams |
| Industry Usage | Used for device simulation, circuit design, and performance prediction | Involved in device development, fabrication, and testing |
Compact Device Modeling focuses on creating simplified models of semiconductor devices for simulation purposes, aiding circuit design. Semiconductor Device Engineers work on designing, developing, and testing actual semiconductor devices. While both roles require engineering expertise and involve semiconductor technology, modeling is more simulation-oriented, whereas engineering involves hands-on device development.
Full-time
Medical, Retirement, PTO
Re-posted 23 days ago
Intel rating
8.7
Based on 146 frontline employees who took The Breakroom Quiz
11th of 142 rated electronics manufacturers
Job description
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.
Life at Intel
About the team and organization: Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies. As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications.
As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel's new technologies.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor's degree in Electrical Engineering or a related discipline and 5+ or
Master's degree in Electrical Engineering or a related discipline and at least 3 years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline.
Graduate coursework or research experience in semiconductor device physics or 5+ years of work experience in Semiconductor device physics.
1+ years' experience Python scripting for data analysis, automation and documentation.
Preferred Qualifications
Ph.D. in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field.
Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA) including experience in one or more of the following areas:
- Experience developing Layout-dependent effects (LDE) for FinFET or GAAFET technologies and their impact on circuit performance.
- Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models.
- Modeling using Open Model Interface (OMI).
- Strong understanding of process flow, layout, and basic circuit design/simulation.
- Modeling self-heating effects and their influence on device and circuit performance.
- Proven capability to collaborate across multiple teams and geographies.
- Experience with machine learning algorithms and their application is data analysis and compact model development.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa ClaraBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968