NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... As part of NVIDIA's "AI for chip design" team, you will have the opportunity to tap into the ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... As part of NVIDIA's "AI for chip design" team, you will have the opportunity to tap into the ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... As part of NVIDIA's "AI for chip design" team, you will have the opportunity to tap into the ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... As part of NVIDIA's "AI for chip design" team, you will have the opportunity to tap into the ...
Digital IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
Medical
Dental
Vision
Retirement
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... As a Digital IC Design Engineer Intern, your responsibilities will include: * Micro-architecture ...
Digital IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
Medical
Dental
Vision
Retirement
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... As a Digital IC Design Engineer Intern, your responsibilities will include: * Micro-architecture ...
Knowledge of the chip design process for design and verification. * Ability to present and explain ... As a Senior Engineer within Google's silicon team, you will help deliver products that have a ...
Knowledge of the chip design process for design and verification. * Ability to present and explain ... As a Senior Engineer within Google's silicon team, you will help deliver products that have a ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ... Spot inefficiencies in the front-end chip implementation process and propose actionable ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ... Spot inefficiencies in the front-end chip implementation process and propose actionable ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ... Spot inefficiencies in the front-end chip implementation process and propose actionable ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ... Spot inefficiencies in the front-end chip implementation process and propose actionable ...
Analog and Mixed-Signal IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
Medical
Dental
Vision
Retirement
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in ...
Analog and Mixed-Signal IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
Medical
Dental
Vision
Retirement
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in ...
We're looking for hardware engineers with hands-on experience in chip design workflows--ideally those who have contributed to real-world tapeouts at companies like Apple, NVIDIA, Etched, or leading ...
Quick apply
We're looking for hardware engineers with hands-on experience in chip design workflows--ideally those who have contributed to real-world tapeouts at companies like Apple, NVIDIA, Etched, or leading ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$180 - $280/hr
Medical
Dental
Vision
# Physical Design Engineer - Full Chip ImplementationEtched • • • 4h agoSave this role or tell us whether you want more jobs like it.**About Etched**Etched is building hardware for frontier ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$180 - $280/hr
Medical
Dental
Vision
# Physical Design Engineer - Full Chip ImplementationEtched • • • 4h agoSave this role or tell us whether you want more jobs like it.**About Etched**Etched is building hardware for frontier ...
Design and Verification Engineer
San Jose, CA · On-site
$150 - $350/hr
Medical
Dental
Vision
Retirement
PTO
Founded by leading experts in AI and chip design, we work with top-20 semiconductor companies ... In this role, you will work side‑by‑side with our AI engineering and research groups to build ...
Design and Verification Engineer
San Jose, CA · On-site
$150 - $350/hr
Medical
Dental
Vision
Retirement
PTO
Founded by leading experts in AI and chip design, we work with top-20 semiconductor companies ... In this role, you will work side‑by‑side with our AI engineering and research groups to build ...
High performance and large chip design experienceispreferred. * Exposure to DFT is preferred ... Engineering Job Level: TCP_05 "The expected salary/wage range for this position is provided below.
High performance and large chip design experienceispreferred. * Exposure to DFT is preferred ... Engineering Job Level: TCP_05 "The expected salary/wage range for this position is provided below.
High performance and large chip design experienceispreferred. * Exposure to DFT is preferred ... Engineering Job Level: TCP_05 "The expected salary/wage range for this position is provided below.
High performance and large chip design experienceispreferred. * Exposure to DFT is preferred ... Engineering Job Level: TCP_05 "The expected salary/wage range for this position is provided below.
High performance and large chip design experienceispreferred. * Exposure to DFT is preferred ... Engineering Job Level: TCP_05 "The expected salary/wage range for this position is provided below.
High performance and large chip design experienceispreferred. * Exposure to DFT is preferred ... Engineering Job Level: TCP_05 "The expected salary/wage range for this position is provided below.
Knowledge of the chip design process and methodology for RTL quality. * Ability to present and ... As a Senior Engineer within Google's silicon team, you will help deliver products that have a ...
Knowledge of the chip design process and methodology for RTL quality. * Ability to present and ... As a Senior Engineer within Google's silicon team, you will help deliver products that have a ...
Contribute to end-to-end chip design workflows, from early architecture definition to final tapeout ... Hands-on programming skills in Python for design automation or tooling. Familiarity with ...
Contribute to end-to-end chip design workflows, from early architecture definition to final tapeout ... Hands-on programming skills in Python for design automation or tooling. Familiarity with ...
Package Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering ... Experience in chip package substrate layout, design verification, DFM and taping out for production.
Package Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering ... Experience in chip package substrate layout, design verification, DFM and taping out for production.
Physical Design Engineer
Cupertino, CA · On-site
$167K - $172K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Engineering. Preferred Qualifications Deep design experience in high PHY and/or SOC designs. Deep ...
Physical Design Engineer
Cupertino, CA · On-site
$167K - $172K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Engineering. Preferred Qualifications Deep design experience in high PHY and/or SOC designs. Deep ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
Physical Design Engineer
Cupertino, CA · On-site
$167K - $172K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Engineering. Preferred Qualifications Deep design experience in high PHY and/or SOC designs. Deep ...
Physical Design Engineer
Cupertino, CA · On-site
$167K - $172K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Engineering. Preferred Qualifications Deep design experience in high PHY and/or SOC designs. Deep ...
Chip Design Engineer information
See California salary details
$40K - $50.6K
2% of jobs
$50.6K - $61.1K
11% of jobs
$66.8K is the 25th percentile. Wages below this are outliers.
$61.1K - $71.7K
23% of jobs
The median wage is $78.5K / yr.
$71.7K - $82.3K
22% of jobs
$82.3K - $92.9K
17% of jobs
$93.2K is the 75th percentile. Wages above this are outliers.
$92.9K - $103.5K
9% of jobs
$103.5K - $114.1K
6% of jobs
$114.1K - $124.7K
3% of jobs
$124.7K - $135.2K
3% of jobs
$135.2K - $145.8K
2% of jobs
$145.8K - $156.4K
1% of jobs
$40K
$87K
$156.4K
How much do chip design engineer jobs pay per year?
As of Aug 15, 2026, the average yearly pay for chip design engineer in California is $86,995.00, according to ZipRecruiter salary data. Most workers in this role earn between $67,100.00 and $97,200.00 per year, depending on experience, location, and employer.
What is the salary of chip design engineer?
The average salary of a chip design engineer varies by experience and location but typically ranges from $80,000 to $150,000 annually. Senior engineers with specialized skills in VLSI design and FPGA development can earn higher salaries, often exceeding $180,000. Certifications and proficiency in tools like Cadence or Synopsys can also influence compensation.
What are some typical projects or daily tasks for a chip design engineer?
As a Chip Design Engineer, your daily tasks often include designing and simulating integrated circuits, reviewing schematics, writing and verifying code in hardware description languages, and collaborating closely with layout engineers and verification teams. You may also participate in design reviews, troubleshoot potential issues, and optimize chip performance to meet specific requirements. Working with cross-functional teams, including software engineers and product managers, is common to ensure the chip integrates seamlessly with end products. This role provides opportunities to see your designs progress from concept to final manufacturing, offering valuable hands-on experience at each stage of development.
What are the key skills and qualifications needed to thrive as a chip design engineer?
To thrive as a Chip Design Engineer, you need a solid background in electrical engineering, digital and analog circuit design, and experience with VLSI principles, usually backed by a relevant degree. Proficiency with industry-standard tools like Cadence, Synopsys, and experience in HDL languages (such as Verilog or VHDL) is highly valued, as are certifications like Certified IC Designer. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set you apart. These competencies are critical for developing reliable, high-performance chips in a collaborative and deadline-driven environment.
What is a chip design engineer?
A Chip Design Engineer is responsible for designing and developing integrated circuits (ICs) used in electronic devices. They work with hardware description languages (HDLs) like Verilog or VHDL to create digital or analog circuit designs. Their role includes logic design, verification, simulation, and testing to ensure performance and power efficiency. They collaborate with teams across hardware, software, and manufacturing to bring chips from concept to production. Chip Design Engineers are essential in industries like consumer electronics, automotive, and telecommunications.
What does a chip design engineer do?
A chip design engineer develops and designs integrated circuits and microchips used in electronic devices. They use electronic design automation (EDA) tools, create schematics, simulate circuit performance, and collaborate with manufacturing teams to ensure the chips meet specifications and quality standards.
How much do chip design engineers make?
Chip design engineers typically earn a median annual salary ranging from $90,000 to $130,000, depending on experience, location, and industry. Senior engineers with specialized skills in VLSI design or FPGA development can earn higher salaries, often exceeding $150,000 annually.
What are popular job titles related to Chip Design Engineer jobs in California?
For Chip Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Chip Design Engineer jobs in California look for?
The top searched job categories for Chip Design Engineer jobs in California are:
What cities in California are hiring for Chip Design Engineer jobs?
Cities in California with the most Chip Design Engineer job openings:
Full-time
Re-posted 20 days ago
Nvidia rating
9.6
Based on 17 frontline employees who took The Breakroom Quiz
7th of 244 rated software companies
Job description
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement the world's leading SoC's and GPU's. As part of NVIDIA's "AI for chip design" team, you will have the opportunity to tap into the unlimited potential of AI and change the landscape of chip design at NVIDIA and throughout the industry. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. Our team operates at the intersection of research, engineering, and product development, transforming innovative ideas and research breakthroughs into real-world solutions. If you're passionate about the latest research and cutting-edge technologies shaping generative AI, this role and team offer a great opportunity to be at the forefront of innovation.
What you'll be doing:
What we need to see:
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking people in the world working for us. We inspire our engineers to build solutions for the problems faced by our customers. Are you creative? Do you love the challenge of continuously crafting the fastest, most efficient GPUs while driving innovation across multiple fields? If so, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 30, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
What you'll be doing:
- As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications.
- As part of the AI for Chip Design team, you will develop agentic AI solutions to craft the micro-architecture, implement the RTL, and deliver a fully verified, synthesis/timing clean design.
- Collaborate and coordinate with other designers as well as tool and flow owners to make sure design guidelines and agentic solutions meet their requirements.
- Make a difference by using AI technologies to tackle complex problems in chip design, driving innovation and meaningful impact across the industry.
- Drive impact by designing and deploying LLM-powered solutions for engineering assistants and multi-turn, multi-modal dialogue systems.
- Stay ahead by engaging with the latest advancements in machine learning and AI to create powerful solutions.
What we need to see:
- Master's or PhD degree in Electrical Engineering, Computer Science/Engineering, or a related field (or equivalent experience).
- 8+ years of meaningful work experience.
- Experience in micro-architecture and RTL development (Verilog) in complex designs.
- Deep understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
- Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
- Proficiency in rapid prototyping using Python with strong foundational knowledge of data structures, algorithms, and software engineering principles.
- Experience with fine-tuning large language models, building advanced multi-agent systems, RAG pipelines and vector databases.
- Strong analytical, communication, and interpersonal skills, with a proven track record to thrive in dynamic, product-focused, and distributed teams.
- A proactive approach to problem-solving and a willingness to acquire new skills and knowledge as needed to achieve results.
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking people in the world working for us. We inspire our engineers to build solutions for the problems faced by our customers. Are you creative? Do you love the challenge of continuously crafting the fastest, most efficient GPUs while driving innovation across multiple fields? If so, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 30, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993