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Cadence Architect Jobs (NOW HIRING)

Cadence

AE, RTL2GDS Architect

San Jose, CA · On-site

Cadence is a technology company that hires and develops leaders and innovators. They are seeking an Architect to serve as a technical leader within their North America Field Applications Team ...

Cadence

Software Security Architect

San Jose, CA · On-site

Cadence is a technology company focused on developing leaders and innovators. They are seeking an experienced Software Security Architect to lead secure software development practices and integrate ...

Cadence

Lead Red Hat Linux Architect

San Jose, CA · On-site

Cadence is a company that hires and develops leaders and innovators in technology. They are seeking a seasoned Lead Red Hat Linux Architect to modernize their enterprise infrastructure into a ...

Cadence Design Systems, Inc.

Software Architect

San Jose, CA · On-site

$267K - $331K/yr

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of ... Define architecture of new features of Power, Timing and distributed optimizers. * Code new modules ...

Cadence Design Systems Inc.

Software Architect

San Jose, CA · On-site

$178K - $331K/yr

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of ... Individual contributor responsibilities will be to architect/design, develop and roll-out highly ...

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All JobsCadence Architect Jobs

Cadence Architect information

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$46.5K

$128.8K

$201.5K

How much do cadence architect jobs pay per year?

As of Jul 17, 2026, the average yearly pay for cadence architect in the United States is $128,756.00, according to ZipRecruiter salary data. Most workers in this role earn between $91,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a Cadence Architect?

A Cadence Architect is a professional who specializes in designing and optimizing workflows, processes, or systems using Cadence, which is a popular open-source orchestration platform for building distributed, scalable, and resilient applications. Their role involves defining the architecture for integrating Cadence into existing infrastructure, ensuring reliability, and improving efficiency. Cadence Architects work closely with development and operations teams to implement best practices, manage workflows, and address scalability or fault-tolerance challenges. They play a crucial role in organizations that rely on complex, distributed systems to ensure seamless execution of business processes.

How does a Cadence Architect typically collaborate with design and verification teams throughout a project?

A Cadence Architect works closely with both design and verification teams to define and optimize the overall EDA (Electronic Design Automation) methodology, ensuring smooth integration of Cadence tools into the workflow. This collaboration involves setting standards for tool usage, troubleshooting tool-related issues, and guiding teams on best practices for digital or analog design flows. Regular meetings and cross-functional reviews are common, allowing the Cadence Architect to address design challenges early and help teams adopt new tool features efficiently. This collaborative environment fosters innovation and enables faster project delivery by aligning the efforts of all stakeholders.

What is the difference between Cadence Architect vs FPGA Designer?

AspectCadence ArchitectFPGA Designer
Required CredentialsBachelor's or higher in Electrical Engineering, VLSI Design, or related fields; certifications in EDA toolsBachelor's or higher in Electrical Engineering, Computer Engineering, or related fields; FPGA-specific certifications
Work EnvironmentDesign and verification of integrated circuits, EDA tool usage, collaboration with design teamsDesign, simulate, and implement FPGA hardware, often using vendor-specific tools and languages
Employer & Industry UsageSemiconductor companies, EDA tool providers, integrated circuit design firmsElectronics manufacturers, FPGA vendors, embedded systems companies

Cadence Architect and FPGA Designer roles share overlapping skills in digital design and EDA tools but differ mainly in scope. Cadence Architect focuses on IC design and verification at the chip level, while FPGA Designers specialize in programmable hardware development. Both roles require strong technical knowledge and collaboration within engineering teams, but their specific tools and project focus vary.

What are the key skills and qualifications needed to thrive as a Cadence Architect, and why are they important?

To thrive as a Cadence Architect, you need deep expertise in digital design, ASIC/FPGA architecture, and experience with EDA tools, particularly the Cadence suite, often backed by a degree in electrical or computer engineering. Familiarity with Cadence tools such as Virtuoso, Genus, and Innovus, as well as scripting languages like TCL and Python, is typically required. Strong problem-solving, communication, and project management skills help you collaborate effectively with cross-functional engineering teams. These skills are essential to ensure high-quality, efficient chip design and successful project delivery in complex semiconductor environments.
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Cadence Architect jobs near you
Infographic showing various Cadence Architect job openings in the United States as of July 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 83% Physical, 4% Hybrid, and 13% Remote job distribution, with an average salary of $128,756 per year, or $61.9 per hour.
AE, RTL2GDS Architect

AE, RTL2GDS Architect

Cadence

San Jose, CA • On-site

Full-time

Re-posted 4 days ago

Job description

Job Summary:
Cadence is a technology company that hires and develops leaders and innovators. They are seeking an Architect to serve as a technical leader within their North America Field Applications Team, focusing on strategic customer engagements and next-generation EDA & Agentic-AI solutions.
Responsibilities:
• Lead technical engagements with customers and partners to achieve best-in-class PPA, working closely with design teams to meet customer success metrics, guiding adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes (3nm and below).
• Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
• Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure.
• Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.
Qualifications:
Required:
• 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• Deep expertise in digital design fundamentals, advanced node implementation (3nm and below), and EDA tool ecosystems.
• Proven track record of leading technical teams and driving customer success at executive levels.
• Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
• Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
• Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and competitive solutions.
Company:
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Founded in 1988, the company is headquartered in San Jose, USA, with a team of 10001+ employees. The company is currently Late Stage.

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