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Asic Design Verification Engineer Jobs (NOW HIRING)

AvicenaTech

ASIC Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create ...

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

... engineering/related degree + 1 year of related experience. * Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and tools.

K2 Space

ASIC Design Verification Engineer

$130K - $200K/yr

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$165K - $241K/yr

Influence ASIC architecture and design to enable robust verification and high-quality silicon ... Experience in scripting (Python, Perl) and C/C++ programming language. Preferred Qualifications

K2 Space

ASIC Design Verification Engineer

Seattle, WA

$130K - $200K/yr

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

K2 Space

ASIC Design Verification Engineer

Seattle, WA · On-site

$130K - $200K/yr

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

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All JobsAsic Design Verification Engineer Jobs

Asic Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do asic design verification engineer jobs pay per year?

As of Jul 17, 2026, the average yearly pay for asic design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by ASIC Design Verification Engineers, and how can they be overcome?

ASIC Design Verification Engineers often encounter challenges such as managing complex verification environments, ensuring thorough coverage, and keeping up with tight project deadlines. Debugging failures in large, intricate designs can be time-consuming and requires strong problem-solving skills. To overcome these challenges, engineers typically rely on robust verification methodologies (such as UVM), effective communication within cross-functional design teams, and continuous learning to stay updated with the latest verification tools and techniques. Collaboration with designers and regular code reviews also help in identifying and resolving issues early in the development cycle.

What are the key skills and qualifications needed to thrive as an ASIC Design Verification Engineer, and why are they important?

To thrive as an ASIC Design Verification Engineer, you need a solid understanding of digital design, verification methodologies (such as UVM or OVM), and a degree in electrical engineering or a related field. Familiarity with hardware description languages (like Verilog or VHDL), simulation tools (like ModelSim or VCS), and scripting languages (such as Python or Perl) is essential, along with experience using version control systems. Strong problem-solving skills, attention to detail, and effective communication are crucial for identifying design issues and collaborating with cross-functional teams. These skills ensure accurate verification, reduce time-to-market, and contribute to the delivery of reliable and high-performance ASIC products.

What does an ASIC Design Verification Engineer do?

An ASIC Design Verification Engineer is responsible for ensuring that application-specific integrated circuits (ASICs) function as intended before they are manufactured. They develop and implement verification plans, create testbenches, and run simulations to identify design errors. Their work involves using hardware description languages (HDLs) like Verilog or VHDL and tools such as UVM to systematically verify design functionality. This role is crucial for catching bugs early, reducing costly mistakes in silicon, and improving product reliability.

What is the difference between Asic Design Verification Engineer vs Asic Design Engineer?

AspectAsic Design Verification EngineerAsic Design Engineer
Primary FocusVerifying the functionality of ASIC designs through testing and simulationDesigning and developing ASIC hardware components and architecture
Skills & CertificationsKnowledge of verification tools, scripting, hardware description languages (HDL), and testing methodologiesProficiency in HDL, digital design, and circuit architecture
Work EnvironmentMostly in verification labs, simulation environments, and testing setupsDesign offices, hardware labs, and development teams
Industry UsageCommonly employed in semiconductor and electronics companies for testing ASICsUsed in chip design companies for creating hardware components

In summary, Asic Design Verification Engineers focus on testing and validating ASIC designs to ensure functionality, while Asic Design Engineers are responsible for creating and developing the ASIC hardware itself. Both roles require knowledge of HDL and are integral to the ASIC development process.

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Asic Design Verification Engineer jobs near you
Infographic showing various Asic Design Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 95% Full Time, 1% Part Time, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.
ASIC Design Verification Engineer

ASIC Design Verification Engineer

AvicenaTech

Sunnyvale, CA • On-site

$159K - $194K/yr

Full-time

Re-posted 17 days ago

Job description

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)
About the role:
Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions. This position requires strong expertise in verification methodology and a commitment to quality.
Responsibilities:
  • Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology).
  • Verification Planning: Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals.
  • Test Case Creation: Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models.
  • Functional Debugging: Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes.
  • Coverage Closure: Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality.
  • Regression Management: Maintain and manage regression suites, optimizing simulation speed and efficiency.
  • Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines.
  • Scripting and Automation: Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency.

Qualifications:
  • Required:
    • Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
    • Experience: 3+ years of professional experience in ASIC/SoC design verification.
    • UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.
    • Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.
    • Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
    • Coverage Driven Methodology: Solid understanding of constrained-random verification and functional/code coverage analysis.
    • Debugging Skills: Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments.
  • Preferred (Nice to Have):
    • Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe.
    • Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques.
    • Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold).
    • Familiarity with low-power verification techniques.
    • Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding.
    • Exposure to physical layer (PHY) or mixed-signal verification concepts.

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