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Asic Design Verification Engineer Internship Jobs in Arizona

Intel

Memory Circuit Design Engineer

Phoenix, AZ

Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp ... Knowledge of the CMOS ASIC design flow. Job Type:Experienced Hire Shift:Shift 1 (United States of ...

AVTC Group

FPGA Engineer

Tucson, AZ · On-site

$122K - $157K/yr

FPGA Engineer Develop FPGA designs including: Xilinx, Altera,and Microsemi. Designs are implemented ... design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or ...

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Asic Design Verification Engineer Internship information

What does an ASIC design verification engineer intern do?

An ASIC Design Verification Engineer Intern assists with testing and validating the functionality of Application-Specific Integrated Circuits (ASICs) during the hardware development process. Their responsibilities typically include writing test benches, developing verification environments, running simulations, and identifying bugs or design flaws before fabrication. Interns often use hardware description languages like Verilog or VHDL and verification methodologies such as UVM. This role is essential to ensure that the final ASIC design meets the required specifications and functions correctly.

What are the key skills and qualifications needed to thrive as an ASIC design verification engineer intern?

To thrive as an ASIC Design Verification Engineer Intern, you typically need a solid background in digital logic design, hardware description languages (HDLs) like Verilog or VHDL, and coursework in computer engineering or electrical engineering. Familiarity with simulation tools (such as ModelSim or Synopsys VCS), scripting languages like Python or Perl, and version control systems is highly valued. Strong analytical thinking, problem-solving abilities, and effective teamwork skills set exceptional candidates apart. These competencies are crucial for ensuring the functionality, reliability, and timely delivery of complex integrated circuits.

What are some typical challenges faced during an ASIC design verification engineer internship, and how can interns effectively address them?

Interns in ASIC design verification often encounter challenges such as understanding complex hardware specifications, learning new verification tools and methodologies, and debugging intricate design issues. To overcome these, it's important to proactively seek guidance from senior engineers, utilize available documentation and training resources, and actively participate in team meetings. Building strong communication skills and staying organized with test plans and bug tracking can also make the workflow smoother and more manageable.

What is the difference between Asic Design Verification Engineer Internship vs Asic Design Engineer?

AspectAsic Design Verification Engineer InternshipAsic Design Engineer
CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's degree in Electrical Engineering or related field
Work EnvironmentInternship program, often in a corporate R&D or design teamFull-time professional role in ASIC design teams
ResponsibilitiesAssisting in verification testbenches, running simulations, learning verification toolsDesigning, implementing, and testing ASIC hardware components
DurationUsually 3-6 monthsFull-time ongoing role

The Asic Design Verification Engineer Internship is an entry-level, temporary position focused on assisting verification tasks, while the Asic Design Engineer role involves full responsibility for ASIC design and development. Internships provide hands-on experience, whereas full engineers lead projects and make design decisions.

What are popular job titles related to Asic Design Verification Engineer Internship jobs in Arizona?

For Asic Design Verification Engineer Internship jobs in Arizona, the most frequently searched job titles are:

What job categories do people searching Asic Design Verification Engineer Internship jobs in Arizona look for?

The top searched job categories for Asic Design Verification Engineer Internship jobs in Arizona are:

What cities in Arizona are hiring for Asic Design Verification Engineer Internship jobs?

Cities in Arizona with the most Asic Design Verification Engineer Internship job openings:

Asic Design Verification Engineer Internship jobs near you
Infographic showing various Asic Design Verification Engineer Internship job openings in Arizona as of August 2026, with employment types broken down into 87% Full Time, 11% Part Time, and 2% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

Physical Verification Engineer

Intel Corporation

Phoenix, AZ • On-site

$135K/yr

Full-time

Medical, Retirement, PTO

Re-posted 17 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

18th of 161 rated electronics manufacturers

Job description

Job Details:
Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.
Key Responsibilities
Physical Verification Support & Issue Resolution
  • Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
  • Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
  • Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations

Technical Content Development & Training
  • Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
  • Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
  • Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies

Verification Methodology Leadership
  • Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)
  • Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations
  • Drive methodology improvements to streamline customer design workflows and enhance verification productivity

Customer Engagement & Technical Excellence
  • Deliver customer-facing technical support with focus on physical verification challenges and solutions
  • Support customers through complex verification issues and advanced process technology adoption
  • Ensure maximum customer satisfaction through expert guidance and responsive technical support

Core Competencies
  • Self-driven and results-oriented with capability to effectively manage multiple complex tasks
  • Strong analytical problem-solving skills for complex physical verification challenges
  • Effective communication skills with experience in collaboration, active listening, and providing constructive feedback

Qualifications:
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
  • US Citizenship required
  • Ability to obtain a US Government Security Clearance
  • Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
  • 3+ years of experience with advanced CMOS processes (22nm and below)
  • 3+ years of combined experience in layout verification and parasitic extraction EDA tools
  • 3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)

Preferred Qualifications
  • Active US Government Security Clearance with a minimum of Secret level
  • Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
  • Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)
  • Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools
  • Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
  • Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
  • Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
  • Customer facing experience

What We Offer
  • Opportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applications
  • Direct customer engagement and technical leadership in advanced semiconductor verification
  • Access to Intel's most advanced foundry technologies and comprehensive verification tool suites
  • Competitive compensation
  • Professional development in physical verification methodologies and foundry services
  • Direct impact on national security through advanced semiconductor verification solutions

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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