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Asic Design Internships Jobs (NOW HIRING)

Etched

DFT Intern

San Jose, CA · On-site

Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals ... Program details * 12-week paid internship * Generous housing support for those relocating * Daily ...

Etched

DFT Intern

San Jose, CA · On-site

Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals ... Program details * 12-week paid internship * Generous housing support for those relocating * Daily ...

Ayar Labs

Engineer, Physical Design

San Jose, CA

$120K - $160K/yr

We are seeking a collaborative Physical Design Engineer to join our high-performance ASIC/SoC team ... Prior internship or co-op experience in a Physical Design or Hardware Engineering role.

Ayar Labs

Engineer, Physical Design

San Jose, CA · On-site

$120K - $160K/yr

We are seeking a collaborative Physical Design Engineer to join our high-performance ASIC/SoC team ... Prior internship or co-op experience in a Physical Design or Hardware Engineering role.

Intel

GPU Physical Design Engineer Lead

Folsom, CA · On-site

$190K - $269K/yr

In this position, the candidate will be part of a team implementing ASIC designs for Integrated ... internship experience and or schoolwork/classes/research. * Bachelor's in Electrical/Computer ...

Intel

GPU Physical Design Engineer Lead

Santa Clara, CA · On-site

$190K - $269K/yr

In this position, the candidate will be part of a team implementing ASIC designs for Integrated ... internship experience and or schoolwork/classes/research. * Bachelor's in Electrical/Computer ...

Marvell

Principal Digital Design Engineer

San Diego, CA

$144K/yr

Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory ... every stage - from internship to retirement and through life's most important moments. Our ...

Intel

DFT Application Engineer

Phoenix, AZ · On-site

... experience, internship experience and / or schoolwork/classes/research. The preferred ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...

Marvell

Staff Physical Design Engineer

Irvine, CA · On-site

$146K - $150K/yr

Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC ... every stage - from internship to retirement and through life's most important moments. Our ...

Marvell

Staff Digital Design Engineer

San Diego, CA

Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory ... every stage - from internship to retirement and through life's most important moments. Our ...

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Asic Design Internships information

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$150.2K

$202K

How much do asic design internships jobs pay per year?

As of Jun 14, 2026, the average yearly pay for asic design internships in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Design Internships vs FPGA Design Internships?

AspectAsic Design InternshipsFPGA Design Internships
Required SkillsHardware description languages (Verilog/VHDL), digital design, ASIC flowFPGA programming, HDL, digital logic, FPGA tools
Work EnvironmentSemiconductor companies, chip design firms, R&D labsElectronics companies, prototyping labs, FPGA vendors
Industry UsageASIC chip development for consumer electronics, automotive, telecomPrototyping, testing, and implementing digital designs on FPGAs

Asic Design Internships focus on designing and developing custom integrated circuits using HDL and ASIC flow, often in semiconductor companies. FPGA Design Internships involve programming and testing digital circuits on FPGA platforms, suitable for rapid prototyping and testing. Both roles require knowledge of HDL but differ in application and environment, with ASIC internships emphasizing chip manufacturing and FPGA internships emphasizing flexible hardware implementation.

More about Asic Design Internships jobs
What cities are hiring for Asic Design Internships jobs? Cities with the most Asic Design Internships job openings:
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What job categories do people searching Asic Design Internships jobs look for? The top searched job categories for Asic Design Internships jobs are:
Asic Design Internships jobs near you
Infographic showing various Asic Design Internships job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

DFT Intern

Etched

San Jose, CA • On-site

Internship

Posted yesterday

Job description

About Etched
Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
  • Familiarity with a hardware description language (Verilog or SystemVerilog)
  • Exposure to ASIC or SoC design concepts
  • Familiarity with digital logic design fundamentals
  • Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
  • Familiarity with scripting in Python, Tcl, or another language
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with
  • Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
  • Experience with Tessent or similar DFT tooling
  • Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
  • Exposure to DFT flow automation or regression infrastructure
  • Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.
Program details
  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Based at our office in San Jose, CA
  • Direct mentorship from industry leaders and world-class engineers
  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com.
How we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

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