Optimize payload design and performance with operation with traffic models/CONOPs. Simulation ... Technical Leadership & Mentorship Mentor, guide junior engineers and interns. Act as technical ...
Optimize payload design and performance with operation with traffic models/CONOPs. Simulation ... Technical Leadership & Mentorship Mentor, guide junior engineers and interns. Act as technical ...
Architecte FPGA
Montreal, QC · On-site
Langage de description materiel VHDL/Verilog et le developpement et verification de FPGA et/ou ASIC ... Le poste requiert un diplome d'une ecole d'ingenieur (Electronique, Aeronautique / Spatial ...
Architecte FPGA
Montreal, QC · On-site
Langage de description materiel VHDL/Verilog et le developpement et verification de FPGA et/ou ASIC ... Le poste requiert un diplome d'une ecole d'ingenieur (Electronique, Aeronautique / Spatial ...
Asic Design Engineer information
See Quebec salary details
$76K - $91.5K
3% of jobs
$91.5K - $107K
7% of jobs
$107K - $122.5K
10% of jobs
$126.6K is the 25th percentile. Wages below this are outliers.
$122.5K - $138K
18% of jobs
The median wage is $146.5K / yr.
$138K - $153.5K
21% of jobs
$167.5K is the 75th percentile. Wages above this are outliers.
$153.5K - $169K
17% of jobs
$169K - $184.5K
9% of jobs
$184.5K - $200K
7% of jobs
$200K - $215.5K
4% of jobs
$215.5K - $231K
3% of jobs
$231K - $246.5K
0% of jobs
$76K
$155K
$246.5K
How much do asic design engineer jobs pay per year?
As of Jul 5, 2026, the average yearly pay for asic design engineer in Quebec is $155,045.00, according to ZipRecruiter salary data. Most workers in this role earn between $128,500.00 and $176,500.00 per year, depending on experience, location, and employer.
What is the difference between Asic Design Engineer vs FPGA Design Engineer?
| Aspect | Asic Design Engineer | FPGA Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Designing custom chips for manufacturing | Developing programmable logic designs for prototyping and deployment |
| Industry Usage | Semiconductor companies, consumer electronics, automotive | Prototyping, testing, and specialized hardware applications |
Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.
How much does an ASIC design engineer make?
The average salary for an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $180,000. Compensation may also include bonuses and stock options in some organizations.
What are some common challenges faced by ASIC Design Engineers during the design and verification phases?
ASIC Design Engineers often encounter challenges such as meeting strict performance and power constraints while ensuring that the design remains within budget and time limits. Debugging complex logic errors during simulation and verification can be particularly demanding, as small mistakes can have significant downstream effects. Additionally, effective communication with cross-functional teams—including software, hardware, and validation engineers—is essential to resolve integration issues and meet project milestones. Adapting to rapidly evolving tools and technologies is also a key part of the role.
Are ASIC design engineers in demand?
ASIC design engineers are in high demand due to the growth of semiconductor technology, consumer electronics, and data centers. They require skills in hardware description languages like VHDL or Verilog and familiarity with EDA tools, making their expertise valuable in industries focused on custom chip development.
What engineer makes $500,000 a year?
An experienced senior ASIC design engineer or hardware engineer working in high-paying industries such as semiconductor or technology companies can earn $500,000 or more annually, especially with bonuses and stock options. These roles typically require advanced skills in digital design, verification, and familiarity with tools like VHDL or Verilog, along with extensive industry experience. Compensation varies based on location, company size, and individual expertise.
What are the key skills and qualifications needed to thrive as an ASIC Design Engineer, and why are they important?
To thrive as an ASIC Design Engineer, you need a solid background in electrical engineering, digital logic design, and proficiency with hardware description languages like Verilog or VHDL, usually backed by a relevant degree. Familiarity with EDA tools such as Synopsys or Cadence and knowledge of simulation and verification methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork set outstanding engineers apart in this role. These skills and qualities are vital for delivering complex, high-performance integrated circuits that meet strict specifications and project deadlines.
What are ASIC Design Engineers?
ASIC Design Engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are custom-built semiconductor chips tailored for specific applications or products. They are responsible for the entire design process, including architecture definition, logic design, verification, synthesis, and sometimes physical layout. Their work is crucial in industries like consumer electronics, telecommunications, automotive, and more, ensuring that devices have optimized performance, power efficiency, and functionality for their intended uses.
What Does an ASIC Design Engineer Do?
An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.
What is the salary of ASIC design engineer?
The salary of an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools tend to earn higher salaries.
More about Asic Design Engineer jobs
What are the most commonly searched types of Asic Design Engineer jobs in Quebec? The most popular types of Asic Design Engineer jobs in Quebec are:
What are popular job titles related to Asic Design Engineer jobs in Quebec? For Asic Design Engineer jobs in Quebec, the most frequently searched job titles are:
What job categories do people searching Asic Design Engineer jobs in Quebec look for? The top searched job categories for Asic Design Engineer jobs in Quebec are:
What are popular job titles related to Asic Design Engineer jobs in QC? For Asic Design Engineer jobs in QC, the most frequently searched job titles are:
Job description
The company provides full relocation support, including immigration assistance, and offers a relocation bonus upon arrival in Montreal. Selected candidates may work remotely during the initial months while their immigration process is being completed; however, the long-term expectation is for the individual to transition to onsite work in Montreal once relocation has been finalized.
Tasks summary:
Architecture Concept & Requirements
Establish functional, performance, environmental and security requirements with mission
stakeholders & CONOPs.
Translate requirements into clear payload performance parameters and maintain bidirectional
traceability throughout the project lifecycle.
Establish with cybersecurity team payloadspecific requirements & embed resilience and
security by design.
Payload Architecture Definition
Define the overall digital regenerative payload architecture (optical/RF ISLs, antenna arrays,
digitizers/ onboard processing, Feeder links, master reference oscillator & clock
synchronizations).
Define Interface Control Documents (ICDs) with spacecraft bus, ground segment and payload
specific subsystems.
Define highspeed databus I/F (Serdes, SpaceWire, SpaceFibre, Ethernet, CAN, fiber).
TradeStudy & Technology RoadMapping
Lead tradeoffs for technologies, ASIC/FPGAs/SoCs, highspeed databus, and onboard
processing algorithms, PVT.
Identify emerging technologies and incorporate them into the company's longterm roadmap.
System Modeling & Performance Simulation
Build endtoend models of the signal chain (optical/RF, analog/digital) using
MATLAB/Simulink, SystemView or Pythonbased toolkits.
Run MonteCarlo and tolerance analyses to verify gain, SNR, dynamic range, spectral
efficiency, G/T, EIRP and other key metrics.
Optimize payload design and performance with operation with traffic models/CONOPs.
Simulation & Analysis
Oversee performance simulations & analysis (Gain, Spurious, Linearity, SNR, dynamic range,
spectral efficiency, pointing, G/T, EIRP...etc.) and tolerance budgeting.
Optimize Payload DC power budget with traffic & utilization models.
Hardware & Firmware
Own systemlevel specifications to hardware designers, review schematics, layouts, thermal &
mechanical interfaces.
Oversee MODCODs selection and onboard processing pipelines; define BIST, timing, latency
and deterministic behavior.
CrossFunctional Coordination, Stakeholder & Program Interaction
Communicate technical status, risk assessments and tradestudy results to senior
management and/or customers or partners.
Act as the primary technical liaison with Electrical, Power, Structures, Thermal, Software,
Ground Segment and Mission Operations teams to resolve integration issues early.
Support payload design authority in System design reviews and Mission Operations
handover.
Support B&P (Phase 0 & pre-phase A).
Integration & Verification (IVV)
Author Payload Verification Master Plan covering unittest, subsystemtest, payloadlevel test,
environmental and electromagnetic compatibility (EMC) test campaigns.
Define testautomation framework setup, testcase definition, results analysis and testreport
certification.
Technical Leadership & Mentorship
Mentor, guide junior engineers and interns.
Act as technical liaison with customers, partners and external vendors
Act as Continuous Improvement stakeholder
Contribute to the company's knowledgebase, process enhancements, and standards development.
Configuration, Documentation & Standards Management
Ensure all artefacts, analysis, software, deliverables and documentation are version controlled
in PLM environment.
Chair design reviews (SRR, PDR, CDR, MRR/TRR...etc.).
Support Technology RoadMapping & Innovation.
On Orbit & Operations Support
Technical support to Mission Operations for routine payload health monitoring, contingency
handling and performance trending.
Lead rootcause investigations for onorbit anomalies; update design baselines and
lessonslearned.
Analyze onorbit telemetry, update filter parameters, and generate performance reports.
Define SOOH and associated operator training.
Required Qualifications:
B.Sc. in Electrical Engineering, Aerospace or Physics (M.Sc. preferred) with 12 + years of digital
regenerative payload system design experience on LEO/MEO missions.
Comprehensive knowledge of digital regenerative communications, SDR, DSP, DVB RCS/SX
protocols, Modulation schemes, Class of Service, Networking, MPLS, 2G, 5G, NTN.
Strong technical writing ability (requirements, ICDs, test procedures, risk reports) and
presentation skills; comfortable interfacing with customers, suppliers and senior leadership.
Strong understanding of aerospace system engineering fundamentals.
Hands-on individual who can support systems integration processes and capability to test
systems and resolve problems.
Experience with Confluence and JIRA.
Demonstrated capability to efficiently work with little supervision.
Ability to distill complex problems to fundamentals to solve with analysis, similarity, or
creativity.
Demonstrate excellent written and oral communication skills in English; knowledge of French
will be considered an asset (Contact with clients outside Quebec and work on deliverables in
English).
Employment Type: FULL_TIME
About Hikinex
Sourced by ZipRecruiter
Hikinex is a multi-channel integrated service provider designed to help Companies scale fast and drive more profit. We leverage diverse resources to provide Superior services at a fraction of the cost.
Industry
Strategic planning consulting services
Company size
51 - 200 Employees
Headquarters location
San Francisco, CA, US
Year founded
2016