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Analog Ic Layout Jobs (NOW HIRING)

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Role: Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team ... Efficiently laying out sensitive RF, Analog and Mixed Signal circuits conforming to all physical ...

Apple

Analog IC Design Engineer

Cupertino, CA

$181K - $318K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$181K - $318K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$126K - $220K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$181K - $318K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$171K - $302K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$171K - $302K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$126K - $220K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$126K - $220K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

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Analog IC Layout information

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$100.5K

$142.4K

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How much do analog ic layout jobs pay per year?

As of Jun 8, 2026, the average yearly pay for analog ic layout in the United States is $142,396.00, according to ZipRecruiter salary data. Most workers in this role earn between $117,500.00 and $139,000.00 per year, depending on experience, location, and employer.

What is the difference between Analog Ic Layout vs Digital IC Layout?

AspectAnalog IC LayoutDigital IC Layout
Design FocusContinuous signal processing, precisionBinary signal processing, logic
ComplexityHigh, due to analog component interactionsModerate to high, depending on logic complexity
Tools & TechniquesSpecialized analog layout tools, parasitic extractionStandard digital EDA tools, place & route
Work EnvironmentCleanroom, high precisionCleanroom, logic optimization

Analog IC Layout involves designing circuits that handle continuous signals with high precision, requiring specialized tools and techniques. Digital IC Layout focuses on binary logic circuits, often with more standardized processes. Both roles demand a strong understanding of semiconductor fabrication and layout design, but they differ in complexity and focus areas.

What are some typical challenges faced by Analog IC Layout engineers when working on complex projects?

Analog IC Layout engineers often encounter challenges related to managing parasitic effects, tight space constraints, and meeting stringent performance specifications. Coordinating closely with circuit designers to ensure optimal placement and routing while minimizing noise and interference is essential. Additionally, adhering to foundry design rules and ensuring first-pass silicon success can be demanding, requiring attention to detail and effective communication within cross-functional teams. Staying updated with evolving process technologies and EDA tools also plays a crucial role in overcoming these challenges.

What are the key skills and qualifications needed to thrive as an Analog IC Layout Engineer, and why are they important?

To thrive as an Analog IC Layout Engineer, you need a solid background in electronics, semiconductor physics, and integrated circuit design, typically supported by a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence Virtuoso, DRC/LVS verification systems, and knowledge of layout design rules are essential. Attention to detail, problem-solving abilities, and strong communication skills help you collaborate effectively with design teams and address complex layout challenges. These skills ensure reliable, high-performance chip designs that meet strict industry standards and project requirements.

What is analog IC layout?

Analog IC layout is the process of physically designing the circuitry for analog integrated circuits on a semiconductor chip. It involves translating circuit schematics into geometric shapes and patterns that define the placement of transistors, resistors, capacitors, and interconnections. The goal is to optimize performance, minimize noise, and ensure manufacturability while meeting design specifications for analog functions such as amplification, filtering, and signal processing.
More about Analog IC Layout jobs
What job categories do people searching Analog Ic Layout jobs look for? The top searched job categories for Analog Ic Layout jobs are:
Analog IC Layout jobs near you
Infographic showing various Analog Ic Layout job openings in the United States as of May 2026, with employment types broken down into 1% Internship, 58% Full Time, 33% Part Time, 1% Temporary, 6% Contract, and 1% Nights. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $142,396 per year, or $68.5 per hour.
Sr. Analog Physical Design Engineer

Sr. Analog Physical Design Engineer

OMNIVISION

Santa Clara, CA

Full-time

Posted 14 days ago

Job description

Job Title: Sr. Analog Physical Design Engineer
 
Job Duties:
 
  • Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC’s performance with minimum silicon area.
  • Conduct cross products column ADC layout comparison and IP layout development and maintenance.
  • Perform RCX extraction of column circuit and critical signals parasitic analysis and propose optimized design to improve column ADC performance and image quality.
  • Conduct image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing.
  • Study design rules for new processes and provide physical design guidelines to the design team. Debug and develop Calibre svrf files when needed.
  • Apply SKILL script to improve productivity and design robustness.
  • Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. 
  • Execute top-level layout and coordinate layout resources and schedules for all modules.
  • Perform floor planning and placements including pad locations, power/clock domain planning, ESD, integration of AMS and digital blocks, and chip-level routing strategy.
  • Lead top-level implementation from floorplan through GDS tape-out. 
  • Develop and maintain layout methodologies and documentation to ensure efficient and consistent design practices. 
 
Requirements:
 
Require Master’s degree or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or a closely related field.
 
Require 2 years of experience in CMOS image sensor IC layout design.
 
Require the following experience or skills:
  • Semiconductor process and device fundamentals, with expertise in addressing advanced technology nodes challenges.
  • Experience in image sensor manufacturing technology, performance metrics, and system-level integration in camera applications. 
  • Experience with industry standard EDA tools, such as Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys Hspice, Design Compiler, IC Compiler, PrimeTime, Laker and P2P. 
  • Front-end and back-end ASIC design flows.
  • Experience in stacked chip process flow and related design considerations.
  • Skills in interpreting physical verification reports (DRC, DFM, ERC, LVS, etc.) and understanding SVRF rule files.
  • Advanced layout skills such as common-centroid layouts, symmetrical layouts, use of dummy devices, matching, ESD, latch-up, antenna effects, etc.
  • Understanding of layout impact on device matching, noise coupling, guard-ring, electromigration, isolation and IR drop.
  • Developing CAD flow automation using scripting languages like Perl, Skill, and Tcl.
  • Expertise in low-power, high-precision, high speed analog layout design techniques.
  • Solving crosstalk challenges between adjacent column ADCs in image sensor circuits.
 
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
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