San Jose, CA · On-site
$159K - $194K/yr
We are looking for Senior Mixed Signal Verification Engineer in San Jose, CA and its a 5 day onsite ... Deep understanding of digital VLSI simulation flow * Deep understanding of mixed-mode and analog ...
San Jose, CA · On-site
$159K - $194K/yr
We are looking for Senior Mixed Signal Verification Engineer in San Jose, CA and its a 5 day onsite ... Deep understanding of digital VLSI simulation flow * Deep understanding of mixed-mode and analog ...
Senior ASIC verification engineer This role has been designed as ''Onsite' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Senior ASIC verification engineer This role has been designed as ''Onsite' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Senior ASIC verification engineer This role has been designed as ''Onsite' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Senior ASIC verification engineer This role has been designed as ''Onsite' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
San Jose, CA · On-site
$159K/yr
Deep understanding of digital VLSI simulation flow * Deep understanding of mixed-mode and analog ... Experience with digital verification, UVM, and waveform debug * Teamwork, dedication, strong ...
San Jose, CA · On-site
$159K/yr
Deep understanding of digital VLSI simulation flow * Deep understanding of mixed-mode and analog ... Experience with digital verification, UVM, and waveform debug * Teamwork, dedication, strong ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single ... Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single ... Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single ... Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single ... Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW ... As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW ... As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW ... As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF ...
San Francisco, CA · On-site
$160K - $195K/yr
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW ... As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single ... Hands on experience with VLSI and digital logic design and verification techniques or formal ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single ... Hands on experience with VLSI and digital logic design and verification techniques or formal ...
Beaverton, OR · On-site
$143K/yr
Description As a formal verification engineer working the complete formal verification for single ... Hands on experience with VLSI and digital logic design and verification techniques or formal ...
Beaverton, OR · On-site
$143K/yr
Description As a formal verification engineer working the complete formal verification for single ... Hands on experience with VLSI and digital logic design and verification techniques or formal ...
San Jose, CA · On-site
$150/hr
TITLE :- Mixed Signal Verification Engineer LOCATION - San Jose, CA DURATION - 12+ Months (High ... REQUIRED SKILLS • BS or BE minimum, 3+ year experiences • Deep understanding of digital VLSI ...
San Jose, CA · On-site
$150/hr
TITLE :- Mixed Signal Verification Engineer LOCATION - San Jose, CA DURATION - 12+ Months (High ... REQUIRED SKILLS • BS or BE minimum, 3+ year experiences • Deep understanding of digital VLSI ...
Austin, TX · On-site
$134K - $164K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...
Austin, TX · On-site
$134K - $164K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...
$115K - $135K/yr
... VLSI design.* Exposure to UVM or object-oriented programming concepts.* Experience writing ... You will receive mentorship from senior verification engineers, gain hands-on exposure to industry ...
$115K - $135K/yr
... VLSI design.* Exposure to UVM or object-oriented programming concepts.* Experience writing ... You will receive mentorship from senior verification engineers, gain hands-on exposure to industry ...
San Diego, CA · On-site
$144K - $176K/yr
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description As a C- Focused Design Verification Engineer, you will be at the center of a ...
San Diego, CA · On-site
$144K - $176K/yr
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description As a C- Focused Design Verification Engineer, you will be at the center of a ...
Austin, TX · On-site
$134K - $164K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...
Austin, TX · On-site
$134K - $164K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...
As an Analog Verification Engineer at Micron Technology, Inc., you willhelp shapeadvanced analog ... Strong knowledge of VLSI circuit design fundamentals. * Advancedproficiencyin Python programming ...
As an Analog Verification Engineer at Micron Technology, Inc., you willhelp shapeadvanced analog ... Strong knowledge of VLSI circuit design fundamentals. * Advancedproficiencyin Python programming ...
$80K - $91.2K
1% of jobs
$91.2K - $102.5K
1% of jobs
$102.5K - $113.7K
1% of jobs
$113.7K - $124.9K
1% of jobs
$131.5K is the 25th percentile. Wages below this are outliers.
$124.9K - $136.1K
35% of jobs
The median wage is $138.3K / yr.
$136.1K - $147.4K
54% of jobs
$147.4K - $158.6K
1% of jobs
$158.6K - $169.8K
1% of jobs
$169.8K - $181K
2% of jobs
$181K - $192.3K
1% of jobs
$192.3K - $203.5K
1% of jobs
$80K
$142.6K
$203.5K
A VLSI Verification Engineer is responsible for ensuring the functionality and correctness of complex semiconductor designs before fabrication. They develop and execute test plans using verification methodologies like UVM, SystemVerilog, or formal verification techniques. Their role includes writing testbenches, running simulations, debugging design issues, and collaborating with design teams to meet specifications. Verification engineers play a crucial role in reducing errors, improving design efficiency, and ensuring the final silicon meets performance and reliability standards.
A VLSI Verification Engineer's daily responsibilities generally include developing testbenches, writing and executing test cases using hardware description languages, and analyzing simulation results to identify and resolve design issues. They collaborate closely with design engineers and software teams to review specifications and ensure comprehensive coverage of verification requirements. In addition, they often document verification plans, participate in code reviews, and contribute to the continuous improvement of verification methodologies. This blend of hands-on technical work and collaborative problem-solving provides variety and drives the quality and functionality of semiconductor products.
A VLSI Verification Engineer should possess a solid understanding of digital and analog circuit design, hardware description languages (such as Verilog or VHDL), and strong analytical skills, typically supported by a degree in electrical or electronics engineering. Familiarity with industry-standard verification tools like UVM, SystemVerilog, and simulators, as well as relevant certifications (e.g., in VLSI design), is highly valuable. Excellent problem-solving abilities, attention to detail, and effective communication skills help engineers work efficiently within multidisciplinary teams. These competencies are critical for identifying design flaws early, ensuring chip functionality, and delivering reliable semiconductor products to market.
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For Vlsi Verification Engineer jobs, the most frequently searched job titles are:
San Jose, CA • On-site
$159K - $194K/yr
Other
Posted 14 days ago
Prodapt ASIC Services (formerly Innovative Logic) provides end-to-end SoC/ASIC, FPGA, and embedded software solutions. Our design services cover the complete lifecycle from RTL to GDSII, covering domains like 3nm node physical design, UVM verification, DFT, and silicon bring-up for 5G, AI, and IoT.
We are looking for Senior Mixed Signal Verification Engineer in San Jose, CA and its a 5 day onsite position
Job Responsibilities:
Required Skills:
Thanks & Regards
Divakar Dhandapani
