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Vlsi Digital Design Verification Engineer Jobs (NOW HIRING)

Retym

VLSI Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Learn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification). Requirements Job requirements: * +5 years of experience as ASIC/VLSI digital design engineer * Strong ...

Retym

ASIC Verification Engineer

Austin, TX · On-site

In depth knowledge in VLSI verification flow, languages and concepts. * Experience in data path or ... Plan and perform the verification of digital design blocks according to the design specification ...

Insilico

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ...

Insilico

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ...

TekClap

Signal Verification Engineer

San Jose, CA · On-site

$159K/yr

We are seeking a highly motivated AMS/DMS Verification Engineer with expertise in mixed-signal ... Digital Design Verification. * Strong understanding of Digital VLSI Simulation Flows . * Solid ...

Retym

ASIC Senior Verification Engineer

Austin, TX · On-site

In depth knowledge in VLSI verification flow, languages and concepts. * Experience in data path or ... Plan and perform the verification of digital design blocks according to the design specification ...

Texas Instruments

Design Verification Engineer

Dallas, TX · On-site

$150 - $200/hr

... digital design and systems engineering teams. Responsibilities include: * Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon ...

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW ... You will interact with the analog/RF design team, digital DV team digital design team, and wireless ...

Texas Instruments

$100 - $125/hr

... digital design and systems engineering teams. Responsibilities include: * Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon ...

Texas Instruments Incorporated

$125 - $150/hr

... digital design and systems engineering teams. Responsibilities include: * Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon ...

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW ... You will interact with the analog/RF design team, digital DV team digital design team, and wireless ...

Lorven Technologies

Design verification Engineer

San Jose, CA · On-site

$158K - $192K/yr

Good understanding of digital design fundamentals * Experience with debug tools (Verdi, DVE, etc.) Good to Have: Exposure to low-power verification (UPF) Experience with AMBA protocols (AXI/AHB/APB)

Redolent, Inc.

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team ... The ideal candidate will be responsible for verifying complex digital designs using advanced ...

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Vlsi Digital Design Verification Engineer information

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$105.5K

$149.2K

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How much do vlsi digital design verification engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for vlsi digital design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What does a VLSI digital design verification engineer do?

A VLSI (Very Large Scale Integration) Digital Design Verification Engineer is responsible for ensuring that digital integrated circuits (ICs) and systems function as intended before they are manufactured. They use various verification methodologies, such as simulation, formal verification, and hardware emulation, to check the correctness of digital designs against specifications. Their role involves creating testbenches, writing and running test cases, debugging failures, and collaborating closely with design engineers. This helps catch and fix design errors early, reducing costly re-spins during chip production.

What are the key skills and qualifications needed to thrive as a VLSI digital design verification engineer, and why are they important?

To thrive as a VLSI Digital Design Verification Engineer, you need a solid understanding of digital design concepts, verification methodologies, and a degree in Electrical or Electronics Engineering. Proficiency with verification tools like SystemVerilog, UVM, simulation environments, and debugging tools is typically required. Strong analytical skills, attention to detail, and effective communication are valuable soft skills that help in identifying design issues and collaborating with cross-functional teams. These skills ensure robust, error-free chip designs and efficient project delivery in the highly technical semiconductor industry.

What are some common challenges faced by VLSI digital design verification engineers, and how can they be addressed?

VLSI Digital Design Verification Engineers often face challenges such as managing complex testbenches, ensuring comprehensive coverage, and keeping up with evolving verification methodologies. Debugging failures in large-scale simulations and balancing tight project deadlines can also be demanding. To address these, engineers typically use automated verification tools, adopt reusable verification IPs, and work closely with design and validation teams for efficient problem-solving. Continuous learning and proactive communication are key to overcoming these challenges and excelling in the role.

What are popular job titles related to Vlsi Digital Design Verification Engineer jobs?

For Vlsi Digital Design Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Vlsi Digital Design Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

VLSI Design Engineer

Austin, TX • On-site

Retym
See more jobs at Retymexternal

$134K - $138K/yr

Full-time

Re-posted 22 days ago

Job description

Description
We are looking for talented and experienced VLSI Design Engineers/Micro-architects.
As an VLSI Digital Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.
Key Responsibilities for a VLSI Design Engineer:
Work closely with Algorithm and Architecture teams
  • Understand and translate high-level algorithmic requirements into efficient hardware implementations.

Learn and analyze relevant protocols and standards
  • Interpret protocol specifications (e.g., Ethernet, etc.) and apply them accurately in design.

Participate in all design stages:
  • Micro-architecture definition
  • RTL coding (using Verilog/SystemVerilog)
  • Synthesis-friendly coding and timing-aware design

Collaborate cross-functionally:
  • Verification team: For testbench development, debug support, and functional coverage closure.
  • DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc.
  • Backend/Physical design team: For floorplanning, timing closure, and routing feedback.

Participate in Design Reviews
  • Present and defend design decisions in peer and formal reviews.

Perform Synthesis and Timing Analysis
  • Generate synthesis constraints (SDC), run synthesis, and analyze timing reports.

Debug and Fix Functional/Timing Issues
  • Collaborate in post-silicon or pre-silicon debug; use waveforms, assertions, and logic analyzers.

Optimize for Area, Power, and Performance (PPA)
  • Identify bottlenecks and opportunities for improvement within RTL.

Documentation
  • Maintain clear design documentation for reusability and reference (e.g., micro-architecture specs, interface docs).

Contribute to IP/SoC Integration
  • Work on integrating design blocks into larger systems and handling system-level interfaces.

Participate in Silicon Bring-up and Validation (optional but valuable)
  • Support bring-up of first silicon and assist with post-silicon validation, if applicable.

Keep up-to-date with Industry Trends and Tools
  • Learn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification).

Requirements
Job requirements:
  • +5 years of experience as ASIC/VLSI digital design engineer
  • Strong Verilog/System-Verilog experience
  • Familiar with simulation tools/environments, verification methodologies
  • Strong team player, solid interpersonal skills
  • Entrepreneurial can-do attitude, self-motivated, able to work independently
  • BS/MS in EE/CE from lead universities

Background in one or more of the following domains is an advantage:
  • Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
  • Design DSP of oriented blocks
  • Ethernet (100G and above)
  • Scripting experience using several of the following: Python, Perl, TCL

Apply