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Vlsi Digital Design Verification Engineer Jobs (NOW HIRING)

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA

Design Verification Engineer Compensation up to $225K DOE + strong benefits + long-term project ... Strong digital logic fundamentals Must have: * Pre-silicon experience only (no post-silicon ...

Apple

C - Focused Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... digital logic design, chip architecture, and microarchitecture Develop complex tests or power ...

Apple

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple

Wireless Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple

Wireless Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Saigepartners

AMD/DMS Verification Engineer

San Jose, CA · On-site

$125 - $150/hr

This role will collaborate closely with RF, analog, and digital design teams to create robust ... Deep understanding of digital VLSI simulation and verification flows. * Strong understanding of ...

Saige Partners

AMD/DMS Verification Engineer

San Jose, CA · On-site

$94 - $155/hr

This role will collaborate closely with RF, analog, and digital design teams to create robust ... Deep understanding of digital VLSI simulation and verification flows. Strong understanding of mixed ...

SambaNova

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

S. in Computer Science, Computer Engineering, or related field * 5+ years relevant industry ... Strong understanding of digital design, SoC architecture, and verification methodologies * Strong ...

COGENT Infotech

Design Verification Engineer

Saratoga, CA · On-site

$150K - $183K/yr

Design Verification Engineer Location: Saratoga, CA (Onsite)-5 days We are seeking a Design ... Experience in planning and executing functional verification strategies for complex digital designs.

Texas Instruments

Design Verification Engineer

Dallas, TX · On-site

$123K - $151K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from ... Strong analog/digital behavior debug skills * Experience with functional verification methodologies ...

Texas Instruments

Design Verification Engineer

Dallas, TX · On-site

$123K - $151K/yr

... digital design and systems engineering teams. Responsibilities include: * Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon ...

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Vlsi Digital Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do vlsi digital design verification engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for vlsi digital design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What does a VLSI digital design verification engineer do?

A VLSI (Very Large Scale Integration) Digital Design Verification Engineer is responsible for ensuring that digital integrated circuits (ICs) and systems function as intended before they are manufactured. They use various verification methodologies, such as simulation, formal verification, and hardware emulation, to check the correctness of digital designs against specifications. Their role involves creating testbenches, writing and running test cases, debugging failures, and collaborating closely with design engineers. This helps catch and fix design errors early, reducing costly re-spins during chip production.

What are the key skills and qualifications needed to thrive as a VLSI digital design verification engineer, and why are they important?

To thrive as a VLSI Digital Design Verification Engineer, you need a solid understanding of digital design concepts, verification methodologies, and a degree in Electrical or Electronics Engineering. Proficiency with verification tools like SystemVerilog, UVM, simulation environments, and debugging tools is typically required. Strong analytical skills, attention to detail, and effective communication are valuable soft skills that help in identifying design issues and collaborating with cross-functional teams. These skills ensure robust, error-free chip designs and efficient project delivery in the highly technical semiconductor industry.

What are some common challenges faced by VLSI digital design verification engineers, and how can they be addressed?

VLSI Digital Design Verification Engineers often face challenges such as managing complex testbenches, ensuring comprehensive coverage, and keeping up with evolving verification methodologies. Debugging failures in large-scale simulations and balancing tight project deadlines can also be demanding. To address these, engineers typically use automated verification tools, adopt reusable verification IPs, and work closely with design and validation teams for efficient problem-solving. Continuous learning and proactive communication are key to overcoming these challenges and excelling in the role.

What are popular job titles related to Vlsi Digital Design Verification Engineer jobs?

For Vlsi Digital Design Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Vlsi Digital Design Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

ASIC / VLSI Engineers

Milpitas, CA

Etech Hi
Recruiting and Staffing Services • 11 - 50 employees
Learn more about Etech Hiexternal

Full-time

Re-posted 9 days ago

Job description

ASIC / VLSI ENGINEERS – RTL / STA / PD / DV (Senior Level)

We are hiring 4 experienced ASIC / VLSI Engineers (8+ years) for permanent, full-time, onsite roles in Silicon Valley supporting advanced semiconductor and AI / networking programs. These roles are within a leading semiconductor design services organization, supporting long-term engagements with tier-1 clients in networking and advanced silicon.


Open roles:

  • RTL Engineer (Networking / Ethernet)
  • STA Engineer
  • Physical Design Engineer
  • Design Verification Engineer


Compensation up to $225K DOE + strong benefits + long-term project stability.

What You Need (All Roles)

  • 8+ years of pre-silicon ASIC / VLSI experience
  • Strong background in RTL-based design environments
  • Experience at the SoC / full-chip level (not IP-only)
  • Solid understanding of ASIC lifecycle (design → tapeout)
  • Scripting experience (Python, Tcl, Perl, etc.)
  • Strong digital logic fundamentals


Must have:

  • Pre-silicon experience only (no post-silicon / firmware-only backgrounds)

Role-Specific Requirements


RTL Engineer (Networking)

  • RTL design + microarchitecture
  • Ethernet (802.3), MAC / PCS / SerDes / PHY
  • High-speed designs (100G+ preferred)
  • Tapeout + productization experience


STA Engineer

  • SoC-level timing analysis & closure
  • PrimeTime, Tempus, or similar


Physical Design Engineer

  • Floorplanning, CTS, routing, signoff
  • Timing, congestion, power optimization


Design Verification Engineer

  • SoC-level verification (required)
  • SystemVerilog / UVM
  • Full verification lifecycle


What Sets You Apart

  • Experience with complex SoC / full-chip tapeouts
  • Ability to work cross-functionally (RTL, DV, PD)
  • Background in advanced nodes (28nm and below preferred)

 

If interested and QUALIFIED, please send resume in Microsoft Word format to: krissid@etechhi.com 


Etech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate.


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About Etech Hi

Sourced by ZipRecruiter

Industry

Recruiting and staffing services

Company size

11 - 50 Employees

Headquarters location

Temecula, CA, US

Year founded

2000

View All Etech Hi Jobs