Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint (SDC) and timing analysis. * Experience with ASIC design flow including LINT, Formal, CDC/RDC, power ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint (SDC) and timing analysis. * Experience with ASIC design flow including LINT, Formal, CDC/RDC, power ...
CPU Formal Verification Engineer
$164.47K - $311.89K/yr
Hands-on experience with hardware modeling languages, including System Verilog or Verilog. * Proficiency in scripting or programming languages such as Python, Perl, C/C++, or TCL. * Experience in ...
CPU Formal Verification Engineer
$164.47K - $311.89K/yr
Hands-on experience with hardware modeling languages, including System Verilog or Verilog. * Proficiency in scripting or programming languages such as Python, Perl, C/C++, or TCL. * Experience in ...
FPGA Engineer
Phoenix, AZ · On-site
$122.70K - $157.60K/yr
Ideal candidates will have a deep understanding of FPGA/ASIC development, VHDL/Verilog, and requirements-based verification, with experience developing firmware for FAA/EASA-certified aerospace ...
Quick apply
FPGA Engineer
Phoenix, AZ · On-site
$122.70K - $157.60K/yr
Ideal candidates will have a deep understanding of FPGA/ASIC development, VHDL/Verilog, and requirements-based verification, with experience developing firmware for FAA/EASA-certified aerospace ...
Pre-Silicon Verification Engineer
Phoenix, AZ · On-site
$122.44K - $232.19K/yr
Proficiency with C/C++ System Verilog coding and debug * Experience with RTL development * Knowledge of system level boot flows and power management. * Experience in Computer-Architecture familiarity
Pre-Silicon Verification Engineer
Phoenix, AZ · On-site
$122.44K - $232.19K/yr
Proficiency with C/C++ System Verilog coding and debug * Experience with RTL development * Knowledge of system level boot flows and power management. * Experience in Computer-Architecture familiarity
Must have knowledge and experience in Verilog/System Verilog design and test bench creation. * Must have excellent debug skills in both functional and gate level simulations * Experience with ...
Must have knowledge and experience in Verilog/System Verilog design and test bench creation. * Must have excellent debug skills in both functional and gate level simulations * Experience with ...
Senior RTL Design Engineer
Phoenix, AZ · On-site
Or a Master's degree in the same field with 7+ years of experience. * 7+ years of experience in RTL design using Verilog, or System Verilog, with strong knowledge of hardware modeling and logic debug ...
Senior RTL Design Engineer
Phoenix, AZ · On-site
Or a Master's degree in the same field with 7+ years of experience. * 7+ years of experience in RTL design using Verilog, or System Verilog, with strong knowledge of hardware modeling and logic debug ...
Ideal candidates will have a deep understanding of FPGA/ASIC development, VHDL/Verilog, and requirements-based verification, with a proven design history in developing firmware for FAA/EASA-certified ...
Ideal candidates will have a deep understanding of FPGA/ASIC development, VHDL/Verilog, and requirements-based verification, with a proven design history in developing firmware for FAA/EASA-certified ...
Ideal candidates will have a deep understanding of FPGA/ASIC development, VHDL/Verilog, and requirements-based verification, with a proven design history in developing firmware for FAA/EASA-certified ...
Quick apply
Ideal candidates will have a deep understanding of FPGA/ASIC development, VHDL/Verilog, and requirements-based verification, with a proven design history in developing firmware for FAA/EASA-certified ...
Experience with a hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools. * Programming experience in at least one language: C/C++, Perl ...
Experience with a hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools. * Programming experience in at least one language: C/C++, Perl ...
... System Verilog * Experience in ASIC or SoC development Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical ...
... System Verilog * Experience in ASIC or SoC development Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical ...
FPGA Engineer
$128.90K - $165.60K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
FPGA Engineer
$128.90K - $165.60K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment ...
Senior FPGA Design Engineer
$122.10K - $168.30K/yr
FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using SystemVerilog coding * Working with Xilinx or Microsemi devices and associated flow tools * Delivering FPGA/ASIC ...
Senior FPGA Design Engineer
$122.10K - $168.30K/yr
FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using SystemVerilog coding * Working with Xilinx or Microsemi devices and associated flow tools * Delivering FPGA/ASIC ...
Modelling experience with System Verilog/Real Modelling/Verilog AMS and coding synthesizable RTL. Qualifications We Prefer * Advanced digital design skills such as experience with Conformal ...
Modelling experience with System Verilog/Real Modelling/Verilog AMS and coding synthesizable RTL. Qualifications We Prefer * Advanced digital design skills such as experience with Conformal ...
Senior Digital Design Engineer
Chandler, AZ · On-site
$133.60K/yr
Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), adhering to architectural specifications and performance requirements. (Verilog/SystemVerilog)
Senior Digital Design Engineer
Chandler, AZ · On-site
$133.60K/yr
Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), adhering to architectural specifications and performance requirements. (Verilog/SystemVerilog)
High Speed Analog Design Engineer
Chandler, AZ · On-site
$198.40K/yr
Develop behavioral models (Verilog-A/AMS) for analog blocks to validate architecture performance * Perform system-level modeling (MATLAB/Simulink) for noise and transfer functions * Conduct design ...
High Speed Analog Design Engineer
Chandler, AZ · On-site
$198.40K/yr
Develop behavioral models (Verilog-A/AMS) for analog blocks to validate architecture performance * Perform system-level modeling (MATLAB/Simulink) for noise and transfer functions * Conduct design ...
PMIC Analog Designer
$198.40K/yr
... MATLAB/Simulink, Verilog-A/AMS) to validate architecture, loop stability, and system performance Drive and participate in critical design reviews and ensure design quality, robustness, and ...
PMIC Analog Designer
$198.40K/yr
... MATLAB/Simulink, Verilog-A/AMS) to validate architecture, loop stability, and system performance Drive and participate in critical design reviews and ensure design quality, robustness, and ...
Lead FPGA Design Engineer
Phoenix, AZ · Hybrid
$122.10K - $168.30K/yr
... or Verilog, both are desirable - Professional knowledge of ASIC /FPGA Radiation Hardening techniques - Strong technical and project and problem-solving skills. - Experience technically managing ...
Lead FPGA Design Engineer
Phoenix, AZ · Hybrid
$122.10K - $168.30K/yr
... or Verilog, both are desirable - Professional knowledge of ASIC /FPGA Radiation Hardening techniques - Strong technical and project and problem-solving skills. - Experience technically managing ...
PMIC Analog Designer
Chandler, AZ · On-site
$198.40K/yr
... MATLAB/Simulink, Verilog-A/AMS) to validate architecture, loop stability, and system performance Drive and participate in critical design reviews and ensure design quality, robustness, and ...
PMIC Analog Designer
Chandler, AZ · On-site
$198.40K/yr
... MATLAB/Simulink, Verilog-A/AMS) to validate architecture, loop stability, and system performance Drive and participate in critical design reviews and ensure design quality, robustness, and ...
PMIC Analog Designer
$198.40K/yr
... MATLAB/Simulink, Verilog-A/AMS) to validate architecture, loop stability, and system performance Drive and participate in critical design reviews and ensure design quality, robustness, and ...
PMIC Analog Designer
$198.40K/yr
... MATLAB/Simulink, Verilog-A/AMS) to validate architecture, loop stability, and system performance Drive and participate in critical design reviews and ensure design quality, robustness, and ...
Engineer, Design Verification Engineering
Chandler, AZ · On-site
$133.90K - $163.50K/yr
System Verilog Assertion for Dynamic and Formal Verification. * Fundamental understanding of Universal Verification Methodology * Working experience with custom digital interfaces (I2C, SPI, UART ...
Engineer, Design Verification Engineering
Chandler, AZ · On-site
$133.90K - $163.50K/yr
System Verilog Assertion for Dynamic and Formal Verification. * Fundamental understanding of Universal Verification Methodology * Working experience with custom digital interfaces (I2C, SPI, UART ...
Verilog information
See Phoenix, AZ salary details
$87.4K - $98.1K
9% of jobs
$98.1K - $108.9K
2% of jobs
$108.9K - $119.6K
2% of jobs
$119.6K - $130.3K
4% of jobs
$134.2K is the 25th percentile. Wages below this are outliers.
$130.3K - $141.1K
22% of jobs
$141.1K - $151.8K
4% of jobs
The median wage is $162.6K / yr.
$151.8K - $162.6K
6% of jobs
$171.9K is the 75th percentile. Wages above this are outliers.
$162.6K - $173.3K
29% of jobs
$173.3K - $184K
9% of jobs
$184K - $194.8K
6% of jobs
$194.8K - $205.5K
6% of jobs
$87.4K
$155K
$205.5K
How much do verilog jobs pay per year?
What is a Verilog job?
What are the key skills and qualifications needed to thrive in the Verilog position, and why are they important?
What does a typical day-to-day workflow look like for someone working with Verilog?
Microchip Technology rating
8.1
Based on 31 frontline employees who took The Breakroom Quiz
39th of 137 rated electronics manufacturers
Job description
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job Description:
Job Description:
The Wireless Solutions Group is seeking an experienced Design Engineer for our next generation high-performance, low-power wireless SoC and attach solutions. In this role, you will be responsible for the design of System-on-Chip (SOC) solutions for wireless applications. You will collaborate closely with cross-functional teams, including verification, analog, validation, and software engineers, to deliver high-quality products. Successful candidate requires strong collaboration across sites and functions, excellent communication, and the ability to thrive in a fast-paced, dynamic environment.
Key Responsibilities:
- Contribute to SOC design from concept to tape-out.
- Implement SOC designs according to micro-architecture specifications and design documentation, performing RTL coding, synthesis, timing analysis, and executing the SOC design flow to ensure IC qualification meets required standards.
- Collaborate with verification teams to ensure thorough design verification according to test plans.
- Work with physical design teams to ensure successful integration and implementation.
- Participate in design reviews to ensure compliance with design standards and project requirements.
- Support the validation team in qualifying silicon ICs and debugging potential issues.
- Contribute to the development and optimization of low-power design techniques and power estimation methodologies.
- Interfacing with external vendors and IP sources to resolve problems.
- Ability to work well in a team and excellent problem solving, verbal and written communication skills.
- Working with members from international design and implementation teams.
Requirements/Qualifications:
Qualifications/Requirements:
- Bachelor's degree in computer engineering, electrical engineering, or related field.
- Minimum 12+ years of experience in digital SOC design, with a focus on low-power design.
- Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint (SDC) and timing analysis.
- Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT concepts, and low-power design techniques.
- Strong understanding of SOC architecture (ARM/MIPS), bus protocols (AMBA, AXI, etc.), and peripheral IPs (USB, Ethernet, I2C, SPI, etc).
- Experience with Bus Matrix design.
- Experience with script Language such as TCL, Perl, and Python.
- Excellent English reading, writing and verbal communication skills.
- Strong analytical and problem-solving skills.
- We are looking for candidates who are self-motivators, energetic, and team players.
Preferred Skills and Experience:
- Master's degree in computer engineering, electrical engineering, or related field.
- Knowledge of Bluetooth/BLE/Wi-Fi communication theory and standard specifications.
- Knowledge of security features and principles of functional safety-compliant design.
- Experience with verification methodologies (UVM/OVM).
- Experience with validation methodologies, including debugging on FPGA and silicon IC boards.
Travel Time:
0% - 25%
Physical Attributes:
Hearing, Seeing, Talking
Physical Requirements:
80% sitting, 10% walking, 10% standing
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
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About Microchip
Sourced by ZipRecruiter
Industry
It services
Company size
10,000+ Employees
Headquarters location
Chandler, AZ, US
Year founded
1989