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Full Time Physical Verification Engineer Jobs in Phoenix, AZ

Intel

Physical Verification Engineer

Phoenix, AZ

$135K/yr

Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...

Intel

CPU Formal Verification Engineer

Phoenix, AZ · On-site

$135K/yr

This is a unique opportunity to collaborate closely with architects, RTL developers, and physical design teams to verify intricate architectural features and drive innovation in modern computing ...

Intel

CPU Formal Verification Engineer

Phoenix, AZ

$135K/yr

This is a unique opportunity to collaborate closely with architects, RTL developers, and physical design teams to verify intricate architectural features and drive innovation in modern computing ...

Intel Corporation

CPU Verification engineer

Phoenix, AZ · On-site

$105.65K - $172.86K/yr

Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and ...

Intel

CPU Verification engineer

Phoenix, AZ

$105.65K - $172.86K/yr

Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and ...

Intel

Pre-Silicon Verification Engineer

Phoenix, AZ · On-site

$122.44K - $232.19K/yr

Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and ...

Intel

CPU Formal Verification Engineer

Phoenix, AZ

$164.47K - $311.89K/yr

Collaborate with architects, RTL developers, and physical design teams to enhance verification efficiency. * Analyze, debug, and resolve issues identified during verification, documenting findings ...

Intel

CPU Formal Verification Engineer

Phoenix, AZ

$135K/yr

Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical ...

Intel

Senior CPU Design Verification Engineer

Phoenix, AZ

$135K - $164.80K/yr

Collaborate crossfunctionally with CPU architects, RTL designers, power/performance teams, and physical design engineers to improve design quality and verification effectiveness. * Influence ...

Intelliswift Software

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Python Programming Language - * Physical Design Develop & own physical design implementation of ... verification in advanced technology nodes Resolve design & flow issues related to physical design ...

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Full Time Physical Verification Engineer information

See Phoenix, AZ salary details

$79.4K

$141.6K

$202.1K

How much do full time physical verification engineer jobs pay per year?

As of May 27, 2026, the average yearly pay for full time physical verification engineer in Phoenix, AZ is $141,608.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,000.00 and $135,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Full Time Physical Verification Engineer, and why are they important?

To thrive as a Full Time Physical Verification Engineer, you need expertise in VLSI design, semiconductor physics, and a degree in electrical or electronics engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, along with knowledge of DRC, LVS, and parasitic extraction checks, is essential. Strong problem-solving skills, attention to detail, and effective communication help engineers collaborate with design teams and resolve complex verification issues. These skills ensure the accuracy and manufacturability of integrated circuit designs, which is critical for successful chip production.

What are some common challenges faced by Full Time Physical Verification Engineers, and how can they be addressed?

Full Time Physical Verification Engineers often encounter challenges such as managing tight project deadlines, debugging complex design rule violations, and ensuring seamless communication with design and layout teams. Staying updated with the latest verification tools and methodologies is essential to efficiently identify and resolve errors. Proactive collaboration and regular cross-team meetings can help address misunderstandings early, while leveraging automation scripts can reduce repetitive tasks and improve accuracy. Continuous learning and seeking feedback from peers are effective strategies to overcome these challenges.

What does a Full Time Physical Verification Engineer do?

A Full Time Physical Verification Engineer is responsible for ensuring that integrated circuit (IC) designs meet all manufacturing requirements before production. Their main tasks include running design rule checks (DRC), layout versus schematic (LVS) checks, and electrical rule checks (ERC) to verify that the physical layout matches the intended circuit and adheres to foundry specifications. They work closely with design, layout, and fabrication teams to identify and resolve any issues that could affect chip functionality or yield. Attention to detail and proficiency with electronic design automation (EDA) tools are essential for this role.

What is the difference between Full Time Physical Verification Engineer vs Physical Design Engineer?

AspectFull Time Physical Verification EngineerPhysical Design Engineer
Primary RoleVerifies physical layouts for manufacturability and design rule complianceCreates and optimizes physical layouts for chip design
Skills & CertificationsKnowledge of DRC, LVS, parasitic extraction; familiarity with EDA toolsExperience with placement, routing, and physical implementation tools
Work EnvironmentDesign verification teams in semiconductor or chip design companiesPhysical implementation teams in IC design firms

While both roles focus on physical aspects of chip design, the Full Time Physical Verification Engineer primarily verifies layouts for correctness, whereas the Physical Design Engineer focuses on creating and optimizing the physical layout. Both roles require similar technical skills and often collaborate closely during the chip development process.

What are popular job titles related to Full Time Physical Verification Engineer jobs in Phoenix, AZ? For Full Time Physical Verification Engineer jobs in Phoenix, AZ, the most frequently searched job titles are:
What job categories do people searching Full Time Physical Verification Engineer jobs in Phoenix, AZ look for? The top searched job categories for Full Time Physical Verification Engineer jobs in Phoenix, AZ are:
Full Time Physical Verification Engineer jobs near you
Physical Verification Engineer

Physical Verification Engineer

Intel Corporation

Phoenix, AZ • On-site

$135K/yr

Full-time

Medical, Retirement, PTO

Posted 9 days ago

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers

Job description

Job Details:
Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.
Key Responsibilities
Physical Verification Support & Issue Resolution
  • Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
  • Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
  • Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations

Technical Content Development & Training
  • Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
  • Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
  • Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies

Verification Methodology Leadership
  • Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)
  • Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations
  • Drive methodology improvements to streamline customer design workflows and enhance verification productivity

Customer Engagement & Technical Excellence
  • Deliver customer-facing technical support with focus on physical verification challenges and solutions
  • Support customers through complex verification issues and advanced process technology adoption
  • Ensure maximum customer satisfaction through expert guidance and responsive technical support

Core Competencies
  • Self-driven and results-oriented with capability to effectively manage multiple complex tasks
  • Strong analytical problem-solving skills for complex physical verification challenges
  • Effective communication skills with experience in collaboration, active listening, and providing constructive feedback

Qualifications:
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
  • US Citizenship required
  • Ability to obtain a US Government Security Clearance
  • Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
  • 3+ years of experience with advanced CMOS processes (22nm and below)
  • 3+ years of combined experience in layout verification and parasitic extraction EDA tools
  • 3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)

Preferred Qualifications
  • Active US Government Security Clearance with a minimum of Secret level
  • Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
  • Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)
  • Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools
  • Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
  • Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
  • Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
  • Customer facing experience

What We Offer
  • Opportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applications
  • Direct customer engagement and technical leadership in advanced semiconductor verification
  • Access to Intel's most advanced foundry technologies and comprehensive verification tool suites
  • Competitive compensation
  • Professional development in physical verification methodologies and foundry services
  • Direct impact on national security through advanced semiconductor verification solutions

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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