Required qualifications include a Bachelor's degree in a related field and proficiency in System Verilog. This position offers competitive compensation and benefits, with a focus on substantial ...
Required qualifications include a Bachelor's degree in a related field and proficiency in System Verilog. This position offers competitive compensation and benefits, with a focus on substantial ...
Hardware Engineer, Early Career
Tempe, AZ · Hybrid
$105.50K - $158.50K/yr
Experience with Verilog and/or System Verilog * Must be able to obtain a United States Secret Clearance * Citizenship: This position requires U.S. citizenship What will help you on the job * Master ...
New
Hardware Engineer, Early Career
Tempe, AZ · Hybrid
$105.50K - $158.50K/yr
Experience with Verilog and/or System Verilog * Must be able to obtain a United States Secret Clearance * Citizenship: This position requires U.S. citizenship What will help you on the job * Master ...
New
FPGA Design/Architect Engineer
Scottsdale, AZ · On-site
$123.90K - $170.80K/yr
Keywords: Scottsdale AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development ...
FPGA Design/Architect Engineer
Scottsdale, AZ · On-site
$123.90K - $170.80K/yr
Keywords: Scottsdale AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development ...
FPGA Design/Architect Engineer
Tempe, AZ · On-site
$117.80K - $162.30K/yr
Tempe AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Tempe, AZ · On-site
$117.80K - $162.30K/yr
Tempe AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Phoenix, AZ · On-site
$122.10K - $168.30K/yr
Phoenix AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Phoenix, AZ · On-site
$122.10K - $168.30K/yr
Phoenix AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Mesa, AZ · On-site
$122K - $168.20K/yr
Mesa AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Mesa, AZ · On-site
$122K - $168.20K/yr
Mesa AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Gilbert, AZ · On-site
$122.60K - $169K/yr
Gilbert AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Gilbert, AZ · On-site
$122.60K - $169K/yr
Gilbert AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development, Digital Signal ...
FPGA Design/Architect Engineer
Chandler, AZ · On-site
$121.10K - $166.90K/yr
Keywords: Chandler AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development ...
FPGA Design/Architect Engineer
Chandler, AZ · On-site
$121.10K - $166.90K/yr
Keywords: Chandler AZ Jobs, FPGA Design Architect Engineer, FPGA, Verilog, VHDL, Xilinx, Altera, Vivado, Intel Quartus, Circuit Board Design Process, Firmware Development, Digital Development ...
FPGA Design Engineer
$65 - $70/hr
... Verilog or VHDL. • Develop and optimize FPGA-based solutions for specific applications. • Collaborate with hardware and software engineers to integrate FPGA • Designs into larger systems.Stay ...
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FPGA Design Engineer
$65 - $70/hr
... Verilog or VHDL. • Develop and optimize FPGA-based solutions for specific applications. • Collaborate with hardware and software engineers to integrate FPGA • Designs into larger systems.Stay ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172.39K - $199.23K/yr
Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models. Product definition involvement. Partial telecommute benefit (2 days/week work from home)
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172.39K - $199.23K/yr
Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models. Product definition involvement. Partial telecommute benefit (2 days/week work from home)
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172.39K - $199.23K/yr
Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models. Product definition involvement. Partial telecommute benefit (2 days/week work from home)
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172.39K - $199.23K/yr
Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models. Product definition involvement. Partial telecommute benefit (2 days/week work from home)
Analog Mixed Signal Modeling & Verification Engineer
Chandler, AZ · On-site
$198.90K/yr
Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS * Develop DMS & AMS test plans, test benches, and verification methodologies to ...
Analog Mixed Signal Modeling & Verification Engineer
Chandler, AZ · On-site
$198.90K/yr
Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS * Develop DMS & AMS test plans, test benches, and verification methodologies to ...
Sr. Staff Analog Mixed Signal Modeling & Verification Engineer
Chandler, AZ · On-site
$133.90K - $163.50K/yr
Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS * Develop DMS & AMS test plans, test benches, and verification methodologies to ...
Sr. Staff Analog Mixed Signal Modeling & Verification Engineer
Chandler, AZ · On-site
$133.90K - $163.50K/yr
Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS * Develop DMS & AMS test plans, test benches, and verification methodologies to ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172.39K - $199.23K/yr
Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models. Product definition involvement. Partial telecommute benefit (2 days/week work from home)
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172.39K - $199.23K/yr
Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models. Product definition involvement. Partial telecommute benefit (2 days/week work from home)
FPGA Engineer (Space)
$164.50K - $246.50K/yr
Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions * Integrate and deploy designs on FPGA and FPGA SoC platforms * Collaborate with team members ...
FPGA Engineer (Space)
$164.50K - $246.50K/yr
Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions * Integrate and deploy designs on FPGA and FPGA SoC platforms * Collaborate with team members ...
FPGA Engineer (Space)
$164.50K - $246.50K/yr
Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions * Integrate and deploy designs on FPGA and FPGA SoC platforms * Collaborate with team members ...
FPGA Engineer (Space)
$164.50K - $246.50K/yr
Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions * Integrate and deploy designs on FPGA and FPGA SoC platforms * Collaborate with team members ...
FPGA Engineer (Space)
Tempe, AZ · On-site
$164.50K - $246.50K/yr
Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions * Integrate and deploy designs on FPGA and FPGA SoC platforms * Collaborate with team members ...
FPGA Engineer (Space)
Tempe, AZ · On-site
$164.50K - $246.50K/yr
Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions * Integrate and deploy designs on FPGA and FPGA SoC platforms * Collaborate with team members ...
Senior Design Verification Engineer
Chandler, AZ · On-site
$133.90K - $163.50K/yr
Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera). * At least 5+ years of experience in silicon design or verification. Preferred Skills and Qualifications: * Able to work closely with ...
Senior Design Verification Engineer
Chandler, AZ · On-site
$133.90K - $163.50K/yr
Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera). * At least 5+ years of experience in silicon design or verification. Preferred Skills and Qualifications: * Able to work closely with ...
DFT Engineer (CE-64000845)
Chandler, AZ · On-site
Experience with Verilog, System Verilog, or VHDL. * Understanding of low power test techniques and architectures. * Knowledge of scripting languages such as Perl, Python, or TCL. * Experience with ...
DFT Engineer (CE-64000845)
Chandler, AZ · On-site
Experience with Verilog, System Verilog, or VHDL. * Understanding of low power test techniques and architectures. * Knowledge of scripting languages such as Perl, Python, or TCL. * Experience with ...
Hardware Engineer, Early Career with Security Clearance
Tempe, AZ · Hybrid
$105.50K - $158.50K/yr
Experience with Verilog and/or System Verilog * Must be able to obtain a United States Secret Clearance * Citizenship: This position requires U.S. citizenship What will help you on the job * Master ...
New
Hardware Engineer, Early Career with Security Clearance
Tempe, AZ · Hybrid
$105.50K - $158.50K/yr
Experience with Verilog and/or System Verilog * Must be able to obtain a United States Secret Clearance * Citizenship: This position requires U.S. citizenship What will help you on the job * Master ...
New
Verilog information
See Phoenix, AZ salary details
$87.4K - $98.1K
9% of jobs
$98.1K - $108.9K
2% of jobs
$108.9K - $119.6K
2% of jobs
$119.6K - $130.3K
4% of jobs
$134.2K is the 25th percentile. Wages below this are outliers.
$130.3K - $141.1K
22% of jobs
$141.1K - $151.8K
4% of jobs
The median wage is $162.6K / yr.
$151.8K - $162.6K
6% of jobs
$171.9K is the 75th percentile. Wages above this are outliers.
$162.6K - $173.3K
29% of jobs
$173.3K - $184K
9% of jobs
$184K - $194.8K
6% of jobs
$194.8K - $205.5K
6% of jobs
$87.4K
$155K
$205.5K
How much do verilog jobs pay per year?
What is a Verilog job?
What are the key skills and qualifications needed to thrive in the Verilog position, and why are they important?
What does a typical day-to-day workflow look like for someone working with Verilog?
Full-time
This job post has expired today. Applications are no longer accepted.
Job description
A leading technology company is seeking a SoC Logic Design Engineer to develop cutting-edge System-on-Chip designs that will drive innovation in computing. Responsibilities include creating RTL designs and performing quality checks, along with collaborating with IP providers. Required qualifications include a Bachelor's degree in a related field and proficiency in System Verilog.
This position offers competitive compensation and benefits, with a focus on substantial contributions to technology advancements. #J-18808-Ljbffr