Self-driven and results-oriented with capability to effectively manage multiple complex tasks * Strong analytical problem-solving skills for complex physical verification challenges * Effective ...
Self-driven and results-oriented with capability to effectively manage multiple complex tasks * Strong analytical problem-solving skills for complex physical verification challenges * Effective ...
Principal Engineer -Verification
Gresham, OR · On-site
$144K/yr
Build verification environments for chip/module level designs using SystemVerilog with UVM ... Manage and Launch regressions using Cadence tools such as Verisium Manager and Xcelium Simulator.
Principal Engineer -Verification
Gresham, OR · On-site
$144K/yr
Build verification environments for chip/module level designs using SystemVerilog with UVM ... Manage and Launch regressions using Cadence tools such as Verisium Manager and Xcelium Simulator.
Principal Engineer -Verification
Gresham, OR · On-site
$144K/yr
Build verification environments for chip/module level designs using SystemVerilog with UVM ... Manage and Launch regressions using Cadence tools such as Verisium Manager and Xcelium Simulator.
Principal Engineer -Verification
Gresham, OR · On-site
$144K/yr
Build verification environments for chip/module level designs using SystemVerilog with UVM ... Manage and Launch regressions using Cadence tools such as Verisium Manager and Xcelium Simulator.
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
$181K - $318K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
$181K - $318K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
$181K - $318K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
$181K - $318K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
$18 - $20/hr
This candidate will work closely with the Revenue Cycle Management department while performing all components in the Insurance Verification process for existing and new clients. The ideal candidate ...
$18 - $20/hr
This candidate will work closely with the Revenue Cycle Management department while performing all components in the Insurance Verification process for existing and new clients. The ideal candidate ...
Design Verification Engineer
$181K - $318K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
$181K - $318K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ... verification methodologies like UVM Experience with C/C++, assembly is a plus Excellent ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ... verification methodologies like UVM Experience with C/C++, assembly is a plus Excellent ...
Design Verification Engineer
$141K - $172K/yr
... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ... verification methodologies like UVM Experience with C/C++, assembly is a plus Excellent ...
Design Verification Engineer
$141K - $172K/yr
... Power management and fabric infrastructure - Memory cache management - Display Subsystem for ... verification methodologies like UVM Experience with C/C++, assembly is a plus Excellent ...
CPU Formal Verification Engineer
Hillsboro, OR · On-site
$148K/yr
In-depth computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management. * Hands on experience with industry standard formal verification ...
CPU Formal Verification Engineer
Hillsboro, OR · On-site
$148K/yr
In-depth computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management. * Hands on experience with industry standard formal verification ...
Preferred Qualifications Experience in processor or power management architecture and verification Experience with system fabric protocols such as AXI In-depth knowledge in design verification ...
Preferred Qualifications Experience in processor or power management architecture and verification Experience with system fabric protocols such as AXI In-depth knowledge in design verification ...
Lead our global product verification team with a strong focus on software quality assurance. Collaborate with peer functional managers, and NPI/NPD product development teams to define and execute ...
Lead our global product verification team with a strong focus on software quality assurance. Collaborate with peer functional managers, and NPI/NPD product development teams to define and execute ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug ...
Preferred Qualifications Experience in processor or power management architecture and verification Experience with system fabric protocols such as AXI In-depth knowledge in design verification ...
Preferred Qualifications Experience in processor or power management architecture and verification Experience with system fabric protocols such as AXI In-depth knowledge in design verification ...
Preferred Qualifications Experience in processor or power management architecture and verification Experience with system fabric protocols such as AXI In-depth knowledge in design verification ...
Preferred Qualifications Experience in processor or power management architecture and verification Experience with system fabric protocols such as AXI In-depth knowledge in design verification ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
Verification Manager information
See Oregon salary details
$3K - $3.6K
1% of jobs
$3.6K - $4.2K
7% of jobs
$4.2K - $4.8K
4% of jobs
$4.8K - $5.4K
3% of jobs
$5.4K - $6K
1% of jobs
$6K - $6.6K
2% of jobs
$7K is the 25th percentile. Wages below this are outliers.
$6.6K - $7.2K
7% of jobs
$7.2K - $7.7K
20% of jobs
The median wage is $7.8K / yr.
$7.7K - $8.3K
24% of jobs
$8.4K is the 75th percentile. Wages above this are outliers.
$8.3K - $8.9K
20% of jobs
$8.9K - $9.5K
9% of jobs
$3K
$7.4K
$9.5K
How much do verification manager jobs pay per month?
As of Jun 28, 2026, the average monthly pay for verification manager in Oregon is $7,422.00, according to ZipRecruiter salary data. Most workers in this role earn between $7,050.00 and $8,458.33 per month, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a Verification Manager, and why are they important?
To thrive as a Verification Manager, you need a solid background in engineering or computer science, experience in verification methodologies (such as UVM or SystemVerilog), and often a relevant degree. Familiarity with hardware description languages, verification tools (e.g., Cadence, Synopsys), and project management software is typically required. Strong leadership, problem-solving abilities, and effective communication distinguish top candidates in this role. These skills ensure efficient verification processes, high-quality deliverables, and seamless collaboration across technical teams.
What are Verification Managers?
Verification Managers are professionals responsible for overseeing the process of ensuring that products, systems, or software meet specified requirements and standards. They lead teams that design and execute tests, troubleshoot issues, and maintain quality assurance protocols. Their role often involves coordinating between engineering, quality, and project management teams to ensure deliverables are accurate and reliable before release. Effective Verification Managers help reduce errors, improve product quality, and ensure compliance with industry regulations.
What is the difference between Verification Manager vs Quality Assurance Manager?
| Aspect | Verification Manager | Quality Assurance Manager |
|---|---|---|
| Primary Focus | Ensuring products meet specifications through testing and validation | Overseeing overall quality processes and standards |
| Certifications | Relevant technical certifications, e.g., ISTQB, Six Sigma | Quality management certifications, e.g., ASQ CQE, Six Sigma |
| Work Environment | Technical teams, testing labs, development settings | Quality departments, cross-functional teams, management |
| Industry Usage | Manufacturing, software, engineering | Manufacturing, software, healthcare, and more |
While both roles focus on product quality, Verification Managers primarily concentrate on testing and validation to confirm specifications are met, whereas Quality Assurance Managers develop and oversee quality systems to ensure overall standards are maintained across processes.
What are some typical challenges faced by a Verification Manager and how can they be addressed?
Verification Managers often face challenges such as managing tight project deadlines, ensuring comprehensive test coverage, and coordinating between cross-functional teams. Balancing the quality and speed of verification processes while keeping up with evolving industry standards can also be demanding. To address these challenges, effective project management, clear communication, and implementing automated verification tools can help streamline processes and improve collaboration. Regular training and staying updated with industry best practices are also key to overcoming common obstacles in this role.
What are the most commonly searched types of Verification jobs in Oregon? The most popular types of Verification jobs in Oregon are:
What are popular job titles related to Verification Manager jobs in Oregon? For Verification Manager jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Verification Manager jobs in Oregon look for? The top searched job categories for Verification Manager jobs in Oregon are:
What cities in Oregon are hiring for Verification Manager jobs? Cities in Oregon with the most Verification Manager job openings:
$148K/yr
Full-time
Medical, Retirement, PTO
Posted 9 days ago
Key responsibilities
Provide technical support to customers on layout verification and parasitic extraction challenges.
Create documentation and deliver technical training presentations to customers and internal teams.
Lead optimization of physical verification flows for advanced CMOS processes.
Intel rating
8.7
Based on 144 frontline employees who took The Breakroom Quiz
10th of 139 rated electronics manufacturers
Job description
Job Details:Job Description: Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.
Key Responsibilities
Physical Verification Support & Issue Resolution
Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations
Technical Content Development & Training
Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies
Verification Methodology Leadership
Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)
Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations
Drive methodology improvements to streamline customer design workflows and enhance verification productivity
Customer Engagement & Technical Excellence
Deliver customer-facing technical support with focus on physical verification challenges and solutions
Support customers through complex verification issues and advanced process technology adoption
Ensure maximum customer satisfaction through expert guidance and responsive technical support
Core Competencies
Self-driven and results-oriented with capability to effectively manage multiple complex tasks
Strong analytical problem-solving skills for complex physical verification challenges
Effective communication skills with experience in collaboration, active listening, and providing constructive feedback
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
3+ years of experience with advanced CMOS processes (22nm and below)
3+ years of combined experience in layout verification and parasitic extraction EDA tools
3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)
Preferred Qualifications
Active US Government Security Clearance with a minimum of Secret level
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)
Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools
Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
Customer facing experience
What We Offer
Opportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applications
Direct customer engagement and technical leadership in advanced semiconductor verification
Access to Intel's most advanced foundry technologies and comprehensive verification tool suites
Competitive compensation
Professional development in physical verification methodologies and foundry services
Direct impact on national security through advanced semiconductor verification solutions
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968