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Verification Engineer Jobs (NOW HIRING)

Design Verification Engineer

Austin, TX · Hybrid

$134.80K - $164.50K/yr

Design Verification Engineer #368877 Duration: 12+ months (Possible Extension-Long Term Project) Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite) Description * As a Design Verification ...

Verification Engineer

San Jose, CA · On-site

$120K - $192K/yr

Bachelor's degree in Electrical/Electronic Engineering, Computer Science * 8+ years of relevant industry experience * Strong expertise in RTL verification methodologies , including System Verilog

Verification Engineer

San Jose, CA · On-site

$120K - $192K/yr

Bachelor's degree in Electrical/Electronic Engineering, Computer Science * 8+ years of relevant industry experience * Strong expertise in RTL verification methodologies , including System Verilog

New

Staff Verification Engineer

Austin, TX · On-site

$134.80K/yr

The Verification Engineer will ensure the fidelity of new highly configurable cores and other related IPs, for clients taking on exciting new use cases-like autonomous driving, 5G networking ...

Verification Engineer (Remote)

Salem, MA · Remote

$148.60K/yr

We're seeking a Verification Engineer to contribute to the validation of advanced chip designs. You'll help create and maintain UVM environments, write tests, and ensure functional coverage for high ...

Verification Engineer

Chaska, MN · On-site

$35 - $37/hr

The Verification Engineer is responsibleforallverificationand validationactivities forthe Immunoassay product line.This includes instrument maintenance,drafting and execution of verificationand ...

GPU Verification Engineer

Westford, MA · On-site

$141.40K/yr

We are now looking for a GPU Verification Engineer. NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the world's leading GPUs. This position offers the opportunity to have real ...

Principal Verification Engineer

Dallas, TX · On-site

$127.80K/yr

The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with ...

Verification Engineer 3

Austin, TX · On-site

$60 - $65/hr

Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block ...

Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

GPU Verification Engineer

Westford, MA · On-site

$141.40K/yr

We are now looking for a GPU Verification Engineer. NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the world's leading GPUs. This position offers the opportunity to have real ...

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site +1

$140.60K/yr

Airspan Careers UVM SYSTEMVERILOG VERIFICATION ENGINEER Location: Warren, New Jersey, Plano, TX or REMOTE U.S. Company: AirSpan Networks About AirSpan AirSpan Networks is a global provider of ...

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Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do verification engineer jobs pay per year?

As of Jun 4, 2026, the average yearly pay for verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What Is a Verification Engineer?

A verification engineer runs tests to ensure products function as expected before they become available to customers. Your job duties as a verification engineer include collaborating with the design team, creating a comprehensive testing process, testing products, providing feedback, and ensuring products are ready on time. The qualifications you need for a career as a verification engineer include a bachelor’s degree in an engineering field, at least two to five years of technical experience, and excellent teamwork skills. You may need Professional Engineer (PE) licensure for some employers.

What are the key skills and qualifications needed to thrive as a Verification Engineer, and why are they important?

To thrive as a Verification Engineer, you need a strong background in digital design, computer engineering, and verification methodologies, typically supported by a degree in electrical or computer engineering. Familiarity with hardware description languages like Verilog or VHDL, simulation tools (e.g., ModelSim, VCS), and verification frameworks such as UVM is essential. Strong analytical thinking, problem-solving abilities, and effective communication are standout soft skills in this role. These competencies ensure the reliable validation of complex hardware designs, reducing errors and improving product quality throughout the development process.

How does a Verification Engineer typically collaborate with design and development teams during a project?

Verification Engineers work closely with hardware and software design teams to ensure that products meet technical specifications and function as intended. They participate in regular design reviews, provide feedback on testability, and develop test plans aligned with design goals. Effective communication and collaboration are essential, as Verification Engineers often need to clarify requirements, report bugs, and suggest design improvements. This cross-functional teamwork helps identify issues early, leading to higher-quality products and more efficient project timelines.

What is the difference between Verification Engineer vs Test Engineer?

AspectVerification EngineerTest Engineer
Primary FocusEnsuring design correctness through simulation and formal methodsExecuting tests on hardware or software to validate functionality
Skills & CertificationsKnowledge of verification tools, scripting, HDL languagesTesting methodologies, scripting, hardware/software knowledge
Work EnvironmentDesign teams, simulation labs, verification environmentsTest labs, hardware setups, software testing environments
Industry UsageElectronics, semiconductor, ASIC/IP developmentElectronics, software, embedded systems

Verification Engineers focus on verifying design correctness through simulation and formal methods, while Test Engineers primarily execute tests on hardware or software to validate functionality. Both roles require technical skills and often overlap, but Verification Engineers are more involved in the design validation process, whereas Test Engineers focus on practical testing and validation in real-world environments.

What cities are hiring for Verification Engineer jobs? Cities with the most Verification Engineer job openings:
What are the most commonly searched types of Verification Engineer jobs? The most popular types of Verification Engineer jobs are:
Who are the top companies hiring for Verification Engineer jobs? The top employers for Verification Engineer jobs are:
What states have the most Verification Engineer jobs? States with the most job openings for Verification Engineer jobs include:
Infographic showing various Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 94% Full Time, 2% Part Time, 1% Temporary, and 3% Contract. Highlights an 93% Physical, 2% Hybrid, and 5% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
Design Verification Engineer

Design Verification Engineer

Xoriant Corporation

Austin, TX • Hybrid

$134.80K - $164.50K/yr

Other

Posted 5 days ago


Job description

Job Title: Design Verification Engineer #368877

Duration: 12+ months (Possible Extension-Long Term Project)

Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite)

Description

  • As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.

Responsibilities

  • Triage regression failures and make testbench updates
  • Debug functional errors in RTL model using simulation and debug tools.
  • Maintain efficient and clean regression status
  • Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
  • Review Architecture and Micro-Architecture specifications.
  • Closely work with Architects and RTL designers.
  • Define, maintain and execute unit level and/or Cluster level verification testplans.
  • Generate and run Testcases on logic simulation models.
  • Code Functional coverage models and System Verilog assertions.
  • Drive Functional Coverage and Code coverage to closure.
  • Integrate C++ reference model into Scoreboards

Requirements

  • 5-15 year s industry experience in a design verification role.
  • Proficient in System Verilog/UVM/OVM, OOP/C++
  • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
  • Experience with code coverage and functional coverage driven verification methodology.
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.
  • Excellent working knowledge of scripting languages such as Python or Perl.
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
  • Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
  • Strong debugging skills
  • Strong programming skills with good understanding of algorithms and data structures
  • Good verbal and written communication skills.