Qualifications We are looking for someone who has: * BS/MS degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field * 3+ years of chip design experience in at ...
Qualifications We are looking for someone who has: * BS/MS degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field * 3+ years of chip design experience in at ...
Qualifications We are looking for someone who has: * BS/MS degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field * 3+ years of chip design experience in at ...
Qualifications We are looking for someone who has: * BS/MS degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field * 3+ years of chip design experience in at ...
Chip Design Engineer
San Francisco, CA · On-site
MS in Electrical Engineering or Computer Science. Why Join Us You will be at the forefront of AI-assisted chip design--a fundamental transformation in how chips are built. Your designs will go into ...
Chip Design Engineer
San Francisco, CA · On-site
MS in Electrical Engineering or Computer Science. Why Join Us You will be at the forefront of AI-assisted chip design--a fundamental transformation in how chips are built. Your designs will go into ...
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field.
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field.
... computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited ... We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used ...
... computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited ... We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used ...
... computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited ... We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used ...
... computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited ... We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used ...
... computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited ... We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used ...
... computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited ... We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used ...
Application Engineer
Rio Rancho, NM · On-site
... computer chip worldwide. Nova operates at the atomic level, delivering unique insights through ... As a Applications Engineer at Nova you will play a key role in implementing and optimizing advanced ...
Application Engineer
Rio Rancho, NM · On-site
... computer chip worldwide. Nova operates at the atomic level, delivering unique insights through ... As a Applications Engineer at Nova you will play a key role in implementing and optimizing advanced ...
Software Engineer
$160K - $240K/yr
What You'll Do * Build and optimize our full-stack developer platform for chip engineers using ... Education: BS/MS in Computer Science, Software Engineering, Mathematics or a related field. Core ...
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Software Engineer
$160K - $240K/yr
What You'll Do * Build and optimize our full-stack developer platform for chip engineers using ... Education: BS/MS in Computer Science, Software Engineering, Mathematics or a related field. Core ...
Software Engineer
Palo Alto, CA · On-site
What You'll Do * Build and optimize our full-stack developer platform for chip engineers using ... Education: BS/MS in Computer Science, Software Engineering, Mathematics or a related field. Core ...
Software Engineer
Palo Alto, CA · On-site
What You'll Do * Build and optimize our full-stack developer platform for chip engineers using ... Education: BS/MS in Computer Science, Software Engineering, Mathematics or a related field. Core ...
Chip Package Signal and Power Integrity Engineer
Sunnyvale, CA · On-site
$196K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience with SI/PI design for chip ...
Chip Package Signal and Power Integrity Engineer
Sunnyvale, CA · On-site
$196K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience with SI/PI design for chip ...
Chip Design and Verification Methodology Engineer
San Francisco, CA · On-site
$160K - $195K/yr
Computer Architecture Fundamentals : You possess a solid understanding of Computer Architecture and ... chip design. * MS or PhD in Electrical Engineering or Computer Science. Why Join Us You will be ...
Chip Design and Verification Methodology Engineer
San Francisco, CA · On-site
$160K - $195K/yr
Computer Architecture Fundamentals : You possess a solid understanding of Computer Architecture and ... chip design. * MS or PhD in Electrical Engineering or Computer Science. Why Join Us You will be ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
What You BringRequired * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
What You BringRequired * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
What You Bring Required * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip ...
What You Bring Required * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip ...
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
MATHEMATICS & STATISTICS STUDENT TRAINEE (COMPUTER & DATA SCIENC with Security Clearance
Fort George G Meade, MD · On-site
As a MATHEMATICS & STATISTICS STUDENT TRAINEE (COMPUTER & DATA SCIENCE) you will be responsible for ... engineering to elementary assignments involving recurring work. This involves assisting with ...
MATHEMATICS & STATISTICS STUDENT TRAINEE (COMPUTER & DATA SCIENC with Security Clearance
Fort George G Meade, MD · On-site
As a MATHEMATICS & STATISTICS STUDENT TRAINEE (COMPUTER & DATA SCIENCE) you will be responsible for ... engineering to elementary assignments involving recurring work. This involves assisting with ...
NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 ... engineers can drive complex tasks and cut ramp time. * Push the limits of what's possible in chip ...
NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 ... engineers can drive complex tasks and cut ramp time. * Push the limits of what's possible in chip ...
Trainee Computer Chip Engineer information
See salary details
$12.74 - $14.29
5% of jobs
$14.29 - $15.84
3% of jobs
$15.84 - $17.40
7% of jobs
$18.44 is the 25th percentile. Wages below this are outliers.
$17.40 - $18.95
14% of jobs
$18.95 - $20.50
9% of jobs
$20.50 - $22.05
7% of jobs
The median wage is $22.41 / hr.
$22.05 - $23.60
16% of jobs
$24.96 is the 75th percentile. Wages above this are outliers.
$23.60 - $25.15
15% of jobs
$25.15 - $26.70
7% of jobs
$26.70 - $28.26
11% of jobs
$28.26 - $29.81
5% of jobs
$12
$22
$29
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Solutions Engineer, AI for Chip Design
On-site
Other
Posted 9 days ago
Job description
Agentrys is an applied research team building the future of chip design. Chips power everything around us, and we believe AI will fundamentally transform how chips are designed.
We are developing Agentic Design Automation, or ADA: self-improving agents with agent-native toolchains that accelerate chip design toward full autonomy. Our work sits at the intersection of AI, EDA, infrastructure, and semiconductor engineering.
Role DescriptionThis is a full-time, on-site position for a Solutions Engineer, AI for Chip Design based in San Jose, CA or Hsinchu, Taiwan. In this role, you will:
- Deploy agentic AI systems into real semiconductor design engineering workflows
- Work directly with leading semiconductor companies to understand design workflows, identify high-value pain points, define success metrics, and validate impact
- Collaborate closely with AI researchers, EDA researchers, infrastructure engineers, and chip design experts to solve challenging design problems
- Turn ambiguous customer problems into working prototypes, production deployments, and reusable product capabilities
- Design evaluations, analyze failures, debug workflows, and improve agent systems through real-world feedback
- Build polished technical demos, customer-facing slides, and compelling proof-of-value presentations
- Independently prototype and rig together quick demos to show what is possible before a full product or engineering team is available
- Anticipate customer needs across verification, RTL, physical design, and custom design, and proactively build toward future applications
- Move fast, learn constantly, and own technical outcomes end-to-end
As a Solutions Engineer, you will help shape both Agentrys' product direction and the future workflows of AI-native chip development. This is a hands-on, customer-facing technical role for someone who combines chip design depth, AI curiosity, strong communication, and startup-level execution.
QualificationsWe are looking for someone who has:
- BS/MS degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field
- 3+ years of chip design experience in at least one of the following areas: design verification, RTL design, physical design, or custom design
- Strong technical credibility with semiconductor engineering teams, with the ability to speak peer-to-peer with design, verification, CAD, and EDA engineers
- Familiarity with generative AI systems, agentic workflows, or multi-agent architectures
- Comfortable working directly with customers, including understanding requirements, presenting technical ideas, and handling open-ended technical discussions
- Strong problem-solving ability in messy, real-world engineering environments
- High energy, adaptability, curiosity, and willingness to learn quickly
- Excellent verbal and written communication skills
- Ability to thrive in a fast-moving, highly collaborative startup environment
You will stand out if you have:
- Experience across multiple parts of the chip design stack, especially RTL design, design verification, and physical design
- Built or deployed agentic AI systems for real chip design, EDA, or semiconductor engineering workflows
- Developed innovative chip design methodologies, EDA algorithms, design automation scripts, or internal productivity tools
- Strong software development and systems skills, with the ability to quickly build prototypes, connect tools, automate flows, and create working demos
- A strong customer presence: outgoing, engaging, confident, and comfortable presenting to senior engineering teams
- Ability to create polished, impressive demo slides and deliver them clearly
- A scrappy, self-sufficient working style — able to make progress without waiting for perfect infrastructure or a large support team
- A speculative, product-oriented mindset — able to anticipate customer pain points and imagine new applications before customers fully articulate them
- Published work in chip design, EDA, AI for hardware, or related technical areas
- Experience working in startup-like environments where speed, ownership, and ambiguity are part of the job
The ideal candidate is a technically deep chip design engineer who is excited about AI, enjoys working with customers, and can translate real semiconductor pain points into working agentic solutions.
You should be credible enough to engage directly with experienced customer engineering teams, energetic enough to lead demos and workshops, and scrappy enough to build prototypes independently. You are not only reacting to customer requests — you are actively thinking ahead about where agentic AI can transform chip design workflows.
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