As a Rebar Detailer Trainee at Nucor, you'll use CAD and creativity to turn blueprints into real ... engineer, placer, and detailer. • Pre-plan all projects for critical path, scope, and schedules ...
As a Rebar Detailer Trainee at Nucor, you'll use CAD and creativity to turn blueprints into real ... engineer, placer, and detailer. • Pre-plan all projects for critical path, scope, and schedules ...
EDA Workflow Optimization Engineer
Santa Clara, CA · On-site
$130K - $154K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Santa Clara, CA · On-site
$130K - $154K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Westford, MA · Hybrid
$115K - $136K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Westford, MA · Hybrid
$115K - $136K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Durham, NC · Hybrid
$107K - $127K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Durham, NC · Hybrid
$107K - $127K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Santa Clara, CA · Hybrid
$130K - $154K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Santa Clara, CA · Hybrid
$130K - $154K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Austin, TX · Hybrid
$110K - $130K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
EDA Workflow Optimization Engineer
Austin, TX · Hybrid
$110K - $130K/yr
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on. * Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow ...
Field Application Engineer
Rio Rancho, NM · On-site
... computer chip worldwide. Nova operates at the atomic level, delivering unique insights through ... As a Applications Engineer at Nova you will play a key role in implementing and optimizing advanced ...
Field Application Engineer
Rio Rancho, NM · On-site
... computer chip worldwide. Nova operates at the atomic level, delivering unique insights through ... As a Applications Engineer at Nova you will play a key role in implementing and optimizing advanced ...
Field Application Engineer
Rio Rancho, NM · On-site
... computer chip worldwide. Nova operates at the atomic level, delivering unique insights through ... As a Applications Engineer at Nova you will play a key role in implementing and optimizing advanced ...
Quick apply
Field Application Engineer
Rio Rancho, NM · On-site
... computer chip worldwide. Nova operates at the atomic level, delivering unique insights through ... As a Applications Engineer at Nova you will play a key role in implementing and optimizing advanced ...
Chip CAD DevOps Engineer, Google Cloud
Sunnyvale, CA · On-site
$62 - $84.75/hr
As a Chip CAD Engineer, you will be working with a highly creative team, innovating new ways to develop hardware, improve upon industry standards, and with the potential to evolve a new paradigm in ...
Chip CAD DevOps Engineer, Google Cloud
Sunnyvale, CA · On-site
$62 - $84.75/hr
As a Chip CAD Engineer, you will be working with a highly creative team, innovating new ways to develop hardware, improve upon industry standards, and with the potential to evolve a new paradigm in ...
Chip Package Signal and Power Integrity Engineer
Sunnyvale, CA · On-site
$196K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience with SI/PI design for chip ...
New
Chip Package Signal and Power Integrity Engineer
Sunnyvale, CA · On-site
$196K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience with SI/PI design for chip ...
New
Software Engineer
Palo Alto, CA · On-site
$160K - $240K/yr
What You'll Do * Build and optimize our full-stack developer platform for chip engineers using ... Education: BS/MS in Computer Science, Software Engineering, Mathematics or a related field. Core ...
Quick apply
Software Engineer
Palo Alto, CA · On-site
$160K - $240K/yr
What You'll Do * Build and optimize our full-stack developer platform for chip engineers using ... Education: BS/MS in Computer Science, Software Engineering, Mathematics or a related field. Core ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
... Engineer to develop and support infrastructure tools for chip design and verification processes ... and computer science theory • Experienced with VLSI frontend design and verification • ...
... Engineer to develop and support infrastructure tools for chip design and verification processes ... and computer science theory • Experienced with VLSI frontend design and verification • ...
Quality Engineer (30224)
Hayward, CA · On-site
$82K - $106K/yr
... computer chip inside. Our customers include the largest semiconductor chip and OEM tool ... As a Quality Engineer (QE) at Pentagon Technologies, your main responsibilities will include the ...
Quality Engineer (30224)
Hayward, CA · On-site
$82K - $106K/yr
... computer chip inside. Our customers include the largest semiconductor chip and OEM tool ... As a Quality Engineer (QE) at Pentagon Technologies, your main responsibilities will include the ...
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
CAD Engineer - PDV
Austin, TX · On-site
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
Austin, TX · On-site
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
DMTS Digital Design Engineer / Chip Lead
$206K - $410K/yr
Basic Qualifications * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
DMTS Digital Design Engineer / Chip Lead
$206K - $410K/yr
Basic Qualifications * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
DMTS Digital Design Engineer / Chip Lead
Boise, ID · On-site
$206K - $410K/yr
Basic Qualifications * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
DMTS Digital Design Engineer / Chip Lead
Boise, ID · On-site
$206K - $410K/yr
Basic Qualifications * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
DMTS Digital Design Engineer / Chip Lead
$206K - $410K/yr
Basic Qualifications * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
DMTS Digital Design Engineer / Chip Lead
$206K - $410K/yr
Basic Qualifications * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field * 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead ...
Trainee Computer Chip Engineer information
See salary details
$12.74 - $14.29
5% of jobs
$14.29 - $15.84
3% of jobs
$15.84 - $17.40
7% of jobs
$18.44 is the 25th percentile. Wages below this are outliers.
$17.40 - $18.95
14% of jobs
$18.95 - $20.50
9% of jobs
$20.50 - $22.05
7% of jobs
The median wage is $22.41 / hr.
$22.05 - $23.60
16% of jobs
$24.96 is the 75th percentile. Wages above this are outliers.
$23.60 - $25.15
15% of jobs
$25.15 - $26.70
7% of jobs
$26.70 - $28.26
11% of jobs
$28.26 - $29.81
5% of jobs
$12
$22
$29
How much do trainee computer chip engineer jobs pay per hour?
Other
Posted 17 days ago