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Temporary Memory Design Engineer Jobs (NOW HIRING)

Intel

Memory Circuit Design Engineer

Santa Clara, CA · On-site

$122.44K - $232.19K/yr

Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... D. in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a ...

Intel

Memory Circuit Design Engineer

Hillsboro, OR

$122.44K - $232.19K/yr

Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... D. in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a ...

Pacer Group

Memory Layout Engineer

Irvine, CA · On-site

Memory Layout Engineer Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ ... Design and implement custom memory layouts for advanced technology nodes, collaborating with ...

Micron

Sr. Design Engineer

San Jose, CA

$168.18K - $238K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Design and Product Engineers in the use of verification tools. Use testbench to create input ...

Micron Technology

Sr. Design Engineer

San Jose, CA · On-site

$168.18K - $238K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Design and Product Engineers in the use of verification tools. Use testbench to create input ...

Intel Corporation

CPU Circuit Design Engineer

Austin, TX · On-site

$122.44K - $232.19K/yr

Join Intel as a CPU Circuit Design Engineer and contribute to designing and advancing cutting-edge ... Key Responsibilities: - Design, develop, and build custom digital circuits, including memory and ...

Intel

CPU Circuit Design Engineer

Austin, TX · On-site

$122.44K - $232.19K/yr

Join Intel as a CPU Circuit Design Engineer and contribute to designing and advancing cutting-edge ... Key Responsibilities: - Design, develop, and build custom digital circuits, including memory and ...

Qualcomm

Memory Control Design Engineer

San Diego, CA · On-site

$115.60K - $173.40K/yr

QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front end of the DDR controller interfaces to the rest of the system ...

Micron

Principal HBM Design Architect

Richardson, TX

As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for nextgeneration highbandwidth memory products. You will ...

Nvidia

Senior Memory System Engineer

Santa Clara, CA · Hybrid

$122.70K - $167.90K/yr

Experience in the design, bring-up and validation for memory failure analysis * Experience with ... class engineering teams are rapidly growing. If you're creative and autonomous, we want to hear ...

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Memory Circuit Design Engineer

Memory Circuit Design Engineer

Intel

Santa Clara, CA • On-site

$122.44K - $232.19K/yr

Full-time

Medical, Retirement, PTO

Posted 3 days ago

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers

Job description

Job Details:Job Description: 

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies.

In this position your responsibilities will include, but may not be limited to:

  • Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.

  • Memory bit-cell and complex periphery IC layout and automation.

  • Memory array/IP design, memory circuit innovation, test-chip design.

  • Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.


The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

Education level:

  • Master's degree OR Ph.D. in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 2 years of professional experience.


Technical Experience:

  • Experience with CMOS ASIC design flow.

  • Custom digital circuit design, simulation, layout design, and verification

  • Experience with EDA tools used for analog, digital and mixed-signal circuit design.

  • Post-Si validation experience


Preferred Qualifications:

  • Master's degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline with 4 years of experience OR Ph. D with 1-2 years of professional experience gained through either internships or full-time employment

  • Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM

  • Design trade-offs between power, performance, and area (PPA)

  • Design technology co-optimization (DTCO)

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa ClaraBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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