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Telecommute Asic Rtl Design Engineer Jobs in Mountain View, CA

Google

RTL Design Engineer, TPU and ML

Sunnyvale, CA · On-site

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

Google

TPU RTL Design Engineer

Sunnyvale, CA · On-site

$159K/yr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

  • Medical

  • Dental

  • Vision

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

  • Medical

  • Dental

  • Vision

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · Hybrid

Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...

Etched

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

  • Medical

  • Dental

  • Vision

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

iFlow Inc

Power Engineer (RTL Design)

Sunnyvale, CA · On-site

ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. * We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling ...

Etched

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

  • Medical

  • Dental

  • Vision

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Google

RTL Design Engineer, TPU

Sunnyvale, CA · On-site

... ASIC design. * Experience interacting with software, system hardware, and other cross-functional ... You will design RTL Intellectual Property (IP) with the focus on management and control subsystem ...

Jobsbridge

ASIC Engineer

San Jose, CA

$194K/yr

ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...

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All JobsTelecommute Asic Rtl Design Engineer JobsTelecommute Asic Rtl Design Engineer Jobs in Mountain View, CA

Telecommute Asic Rtl Design Engineer information

See Mountain View, CA salary details

$110.9K

$177.2K

$238.3K

How much do telecommute asic rtl design engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for telecommute asic rtl design engineer in Mountain View, CA is $177,183.00, according to ZipRecruiter salary data. Most workers in this role earn between $155,100.00 and $212,300.00 per year, depending on experience, location, and employer.

What are some common challenges faced by telecommute ASIC RTL design engineers, and how can they be addressed?

Telecommute ASIC RTL Design Engineers often face challenges like coordinating effectively with remote teams, ensuring version control integrity, and maintaining clear communication on project specifications. These challenges can be mitigated by utilizing robust collaboration tools, adhering to standardized documentation practices, and scheduling regular virtual meetings for design reviews. Additionally, staying proactive in seeking feedback and clarifying requirements helps ensure alignment and prevents costly design iterations.

What are the key skills and qualifications needed to thrive as a telecommute ASIC RTL design engineer?

To thrive as a Telecommute ASIC RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, as well as experience with simulation, synthesis, and debugging environments, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills are crucial for collaborating remotely and ensuring design accuracy. These skills are vital to deliver complex, high-performance ASICs on schedule while working efficiently in a remote setting.

What is a telecommute ASIC RTL design engineer?

A Telecommute ASIC RTL Design Engineer is a professional who specializes in designing digital circuits at the Register Transfer Level (RTL) for Application-Specific Integrated Circuits (ASICs), while working remotely. They use hardware description languages like Verilog or VHDL to create and verify circuit designs tailored to specific applications. Their responsibilities often include developing, simulating, and optimizing digital logic, collaborating with cross-functional teams, and ensuring that the final silicon meets design specifications. Since the role is telecommute, all work is performed from a remote location using digital communication and collaboration tools.

What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?

AspectTelecommute Asic Rtl Design EngineerTelecommute Digital IC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL codingBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design
Work EnvironmentRemote, primarily designing RTL code for ASICsRemote, focusing on digital IC architecture and design
Industry UsageCommon in semiconductor and electronics companies

Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Mountain View, CA?

The most popular types of Asic Rtl Design Engineer jobs in Mountain View, CA are:

What cities near Mountain View, CA are hiring for Telecommute Asic Rtl Design Engineer jobs?

Cities near Mountain View, CA with the most Telecommute Asic Rtl Design Engineer job openings:

Telecommute Asic Rtl Design Engineer jobs near you
Infographic showing various Telecommute Asic Rtl Design Engineer job openings in Mountain View, CA as of June 2026, with employment types broken down into 84% Full Time, 4% Part Time, 8% Contract, and 4% Nights. Highlights an 91% Physical, 7% Hybrid, and 2% Remote job distribution, with an average salary of $177,183 per year, or $85.2 per hour.

Senior ASIC Design Engineer

Ethan Alexander Group

San Francisco, CA

Full-time

Re-posted 18 days ago

Job description

ASIC Design Engineer


Responsibilities:


  • Define and bring up FPGA platforms for pre-silicon validation and software development
  • Map ASIC RTL to FGPA while minimizing code base differences
  • Create and execute test plans for validating SoC functionality and performance
  • Resolve challenging system level issues that span multiple disciplines
  • Design logic starting from specification or high level feature description


Requirements:


  • Minimum of 5 years of relevant experience.
  • Scripting or programming experience in Python or C/C++
  • Ability to write and analyze the completeness of constraints
  • Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters
  • Strong analytical and debugging skills
  • BS in Electrical Engineering or equivalent required, MS preferred


Nice to Have:


  • Familiarity with Xilinx FPGA’s and Vivado tool chain
  • Experience with validating and debugging low-power wireless systems
  • Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB)
  • Knowledge of wireless protocols (e.g. Bluetooth Low Energy)