ZipRecruiter

Log In

1

Summer Digital Logic Design Jobs (NOW HIRING)

Apple

Wireless MAC Design Engineer

Sunnyvale, CA

$184K - $324K/yr

Digital logic design fundamentals. Demonstrated experience in translating functional requirements into synthesizable Verilog or SystemVerilog RTL. Knowledge of digital design flows such as RTL ...

Apple

Wireless MAC Design Engineer

Sunnyvale, CA

$129K - $225K/yr

Excellent understanding of digital logic design fundamentals. Ability to translate functional requirements into synthesizable Verilog or SystemVerilog RTL. Knowledge of digital design flows such as ...

Ampere Computing LLC

Logic Engineer

Portland, OR · On-site

$118K - $177K/yr

Relevant internships or academic projects involving digital logic design, microarchitecture, or SoC development * Familiarity with hardware description languages such as System Verilog or VHDL and ...

Taara Connect, Inc

FPGA Design Engineer

Sunnyvale, CA · On-site

$144K - $198K/yr

As an FPGA Design Engineer , you will be responsible for the full lifecycle of FPGA designs - design, simulation, implementation, testing, and verification - for digital logic for high-data-rate ...

OMNIVISION

Digital Design Engineer

Irvine, CA

Design and implement sensor timing control logic and contribute to ISP system-level integration ... Collaborate closely with CIS project leads and sensor digital/analog engineers for system ...

OMNIVISION

Digital Design Engineer

Irvine, CA · On-site

$110K - $140K/yr

Design and implement sensor timing control logic and contribute to ISP system-level integration ... Collaborate closely with CIS project leads and sensor digital/analog engineers for system ...

Lyte

Senior Logic Design Engineer

Sunnyvale, CA · On-site

$170K - $250K/yr

As a Digital Design Engineer, you will work in cooperation with other teams to define SoCs ... Experience in logic Synthesis * Strong analytical and problem-solving skills * Excellent written ...

OMNIVISION

Digital Design Engineer

Irvine, CA · On-site

$110K - $140K/yr

Design and implement sensor timing control logic and contribute to ISP system-level integration ... Collaborate closely with CIS project leads and sensor digital/analog engineers for system ...

previous page

Showing results 41-60

All JobsSummer Digital Logic Design Jobs

Summer Digital Logic Design information

See salary details

$80.5K

$139.4K

$182.5K

How much do summer digital logic design jobs pay per year?

As of Jul 24, 2026, the average yearly pay for summer digital logic design in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Summer Digital Logic Design vs Summer Electrical Engineering?

AspectSummer Digital Logic DesignSummer Electrical Engineering
Required CredentialsTypically requires coursework or experience in digital systems, logic design, and computer architectureRequires broader electrical engineering fundamentals, including circuits, signals, and systems
Work EnvironmentPrimarily focused on digital circuit development, FPGA/ASIC design, and logic simulationEncompasses various electrical systems, power, and electronics projects
Employer & Industry UsageUsed mainly in tech companies, semiconductor firms, and hardware startupsCommon across power, electronics, and telecommunications industries

Summer Digital Logic Design focuses on digital circuit development and logic systems, often within tech and hardware sectors. In contrast, Summer Electrical Engineering covers a broader range of electrical systems, including power and electronics, suitable for diverse industries. Both roles require foundational engineering knowledge but differ in specialization and application.

What are the key skills and qualifications needed to thrive as a Summer Digital Logic Design Engineer, and why are they important?

To thrive as a Summer Digital Logic Design Engineer, you need a solid understanding of digital circuit fundamentals, Boolean algebra, and hardware description languages (such as VHDL or Verilog), often supported by coursework in electrical or computer engineering. Familiarity with simulation tools like ModelSim, FPGA development platforms, and schematic capture software is typically required. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These abilities enable you to design, test, and optimize digital circuits efficiently, ensuring robust and reliable system performance in collaborative engineering environments.

What types of projects or tasks can I expect to work on as a Summer Digital Logic Design intern?

As a Summer Digital Logic Design intern, you will typically engage in hands-on projects involving the design, simulation, and verification of digital circuits, such as creating components for FPGAs or ASICs. Your daily tasks may include writing and debugging code in hardware description languages like Verilog or VHDL, running simulations to test logic functionality, and collaborating with experienced engineers during design reviews. You'll also learn to use specialized tools for schematic capture, synthesis, and timing analysis. This role provides excellent exposure to the practical aspects of hardware development and teamwork within an engineering environment.

What is a Summer Digital Logic Design job?

A Summer Digital Logic Design job is typically an internship or temporary position focused on working with digital circuits and systems during the summer months. Individuals in this role help design, analyze, and test logic circuits using digital components such as logic gates, multiplexers, and flip-flops. They often use hardware description languages like VHDL or Verilog and simulation tools to create and verify digital designs. This position is ideal for students or recent graduates in electrical engineering or computer engineering who want hands-on experience in digital system design.
More about Summer Digital Logic Design jobs
What cities are hiring for Summer Digital Logic Design jobs? Cities with the most Summer Digital Logic Design job openings:
What are the most commonly searched types of Digital Logic Design jobs? The most popular types of Digital Logic Design jobs are:
What states have the most Summer Digital Logic Design jobs? States with the most job openings for Summer Digital Logic Design jobs include:
What job categories do people searching Summer Digital Logic Design jobs look for? The top searched job categories for Summer Digital Logic Design jobs are:
Summer Digital Logic Design jobs near you
Infographic showing various Summer Digital Logic Design job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $139,368 per year, or $67 per hour.

Digital - SerDes Digital Design Lead

Eliyan

Mundelein, IL

$138K/yr

Full-time

Posted 4 days ago

Job description

Join the leading chiplet startup!  As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility.  You will lead the digital design of SerDes transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products.  You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.  We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines
  • Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic
  • Architect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets
  • Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes
  • Collaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up
  • Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules
  • Define and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3
  • Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications
  • Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards
  • Design firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug
  • Support post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates
  • Strong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologies
  • Expert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling
  • Strong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIe
  • Hands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power
  • Experience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environments
  • Demonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environments
  • Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.