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Sta Static Timing Analysis Engineer Jobs in Colorado

Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Perform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or ...

Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Perform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or ...

... static timing analysis tool. Preferably Synopsys PrimeTime and/or Cadence Tempus. * Ability to ... STA requires a person with strong engineering capabilities and good engineering judgement.

... static timing analysis tool. Preferably Synopsys PrimeTime and/or Cadence Tempus. * Ability to ... STA requires a person with strong engineering capabilities and good engineering judgement.

Design Engineer - STA

Fort Collins, CO · On-site

$99K - $135K/yr

... static timing analysis tool. Preferably Synopsys PrimeTime and/or Cadence Tempus. * Ability to ... STA requires a person with strong engineering capabilities and good engineering judgement.

ASIC Physical Design Engineer

Boulder, CO · On-site

$143K - $147K/yr

Our inclusive engineering culture is hardworking, inquisitive, and always eager to learn and grow ... Perform static timing analysis and timing verification across multiple modes and corners, resolving ...

Experience using a static timing analysis tool. * Preferably Synopsys PrimeTime and/or Cadence ... Understanding of basic STA concepts * Solid understanding of RC networks and how they affect the ...

ASIC Physical Design Engineer

Boulder, CO · On-site

$143K - $147K/yr

ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This ... Perform static timing analysis and timing verification across multiple modes and corners, resolving ...

ASIC Physical Design Engineer

Boulder, CO · On-site

$141K - $145K/yr

... static timing analysis and timing verification across multiple modes and corners, resolving setup, hold, clocking, and constraint-related issues to achieve timing closure. • Support physical ...

... STA Engineer. Key Responsibilities * Work with design teams to understand and debug constraints ... Perform deep analysis of timing paths to identify key issues. * Implement timing infrastructure.

STA Engineer

Fort Collins, CO · On-site

$199K/yr

... STA Engineer.As part of APD, you'll help design and manufacture next-generation, high-performance ... Deep analysis of timing paths to identify key issues is critical * Implement timing infrastructure

STA Engineer

Fort Collins, CO · On-site

$199K/yr

... STA Engineer. As part of APD, you'll help design and manufacture next-generation, high-performance ... Deep analysis of timing paths to identify key issues is critical * Implement timing infrastructure

Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level, is a must Implementation experience and knowledge ...

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Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are popular job titles related to Sta Static Timing Analysis Engineer jobs in Colorado?

For Sta Static Timing Analysis Engineer jobs in Colorado, the most frequently searched job titles are:

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The top searched job categories for Sta Static Timing Analysis Engineer jobs in Colorado are:

What cities in Colorado are hiring for Sta Static Timing Analysis Engineer jobs?

Cities in Colorado with the most Sta Static Timing Analysis Engineer job openings:

Design Engineer - STA

Fort Collins, CO • On-site

Broadcom
Semiconductor and Electronic Component Manufacturing • 10K+ employees

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 20 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz


Job description

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Job Description:

Be part of the Custom Silicon Design Team within Broadcom's ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.

Role Overview

This STA Engineering role focuses on chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes and involves working across multiple design hierarchies to define, validate, and sign off complex timing environments for AI, computing, and networking SoCs.

Key Responsibilities

  • Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.

  • Perform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or Cadence Tempus.

  • Define and execute timing signoff methodologies, including process corners, derates, and uncertainties.

  • Conduct pre- and post-route timing analysis, quality of results (QoR) evaluations, and closure verification.

  • Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.

  • Automate timing flows and analysis using Tcl and scripting languages such as Perl or Python.

  • Collaborate with physical design, synthesis, and clock teams to ensure timing convergence and cross-domain consistency.

  • Analyze and debug timing violations, signal integrity issues, and clock network challenges.

  • Support power and performance optimization through informed timing analysis and constraint tuning.

  • Ensure full compliance with timing signoff checklists, methodology, and documentation.

Technical Skills / Background

  • Deep understanding of VLSI design principles and ASIC physical design fundamentals.

  • Working knowledge of PLLs, clock network design, and timing elements such as flip-flops, latches, and memories.

  • Proficiency in timing constraint creation, debugging, and validation.

  • Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.

  • Familiar with setup/hold analysis, multi-mode multi-corner (MMMC) timing, and ECO convergence.

  • Exposure to advanced STA techniques, including POCV/SOCV/LVF, PBA, and SPICE correlation.

  • Knowledge of timing libraries (CCS/ECSM/NLDM) and multi-input switching (MIS) effects.

Coding & Tool Proficiency

  • Strong experience with Tcl scripting and Linux/UNIX environments.

  • Proficiency in Python, Perl, or Ruby preferred.

  • Hands-on experience with Synopsys and/or Cadence STA tools highly desirable.

Collaboration and Leadership

  • Excellent communication, analytical, and problem-solving abilities.

  • Ability to work effectively with external customers, cross-functional and global design teams.

  • Skilled at organizing and presenting large data sets, prioritizing tasks, and driving to closure.

  • Demonstrates independent decision-making and strong engineering judgment.

  • Provides technical leadership, mentoring, and initiative in methodology improvements.

Education and Experience

  • BS in Electrical or Computer Engineering with 8+ years of relevant experience, or

  • MS in Electrical or Computer Engineering with 6+ years of relevant experience.


Compensation and Benefits


The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.


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