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What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

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Sta Static Timing Analysis Engineer jobs near you

DFT ATPG Design and Test Engineer

Fort Collins, CO • On-site

Advanced Micro Devices, Inc
Computer and Electronic Product Manufacturing • 5 - 10K employees
Learn more about Advanced Micro Devices, Incexternal

$126K/yr

Full-time

Posted 15 days ago

Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we'll advance your career.
THE ROLE:
The Cores Organization develops high-performance CPU cores and cache technologies that power AMD's server, client, and gaming products. We are seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation cores and caches.
In this role, you will own scan test pattern delivery, support product test bring-up, improve scan architecture and coverage, and partner closely with design, physical design, and product test teams to solve complex technical challenges and improve product quality.
THE PERSON:
You are an analytical, detail-oriented engineer who enjoys solving complex technical problems and driving continuous improvement. You take ownership of long-term deliverables, communicate effectively across teams, and challenge established approaches to improve quality and execution. You are eager to expand your knowledge of CPU and cache technologies and thrive in a collaborative environment that values innovation, learning, and technical growth.
KEY RESPONSIBILITIES:
  • Own the generation, validation, and delivery of scan test patterns for next-generation CPU cores and caches.
  • Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
  • Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
  • Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
  • Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
  • Address DFT requirements for high-frequency CPU designs while minimizing performance impact.
  • Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
  • Develop and implement improvements that simplify design complexity and strengthen engineering quality.
  • Contribute to the continued evolution of CPU cache array and DFT design practices.

PREFERRED EXPERIENCE:
  • Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.
  • Strong working knowledge of industry-standard ATPG tools and their application to pattern generation, fault coverage, and product quality.
  • Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
  • Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.
  • Experience with multi-clock and multi-power-domain designs.
  • Familiarity with static timing analysis, clock-domain crossing analysis, static power analysis, and physical design closure.
  • Experience adapting standard DFT tools or methods to meet the performance requirements of complex, high-frequency designs.
  • CPU or cache architecture experience is preferred; strong DFT candidates from related ASIC environments may also be considered.
  • Demonstrated success collaborating across design, physical design, product engineering, and geographically distributed teams.
  • Interest in continuous improvement and in developing broader expertise across CPU, cache, and silicon design disciplines.

ACADEMIC CREDENTIALS:
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field is preferred.

This role is not eligible for visa sponsorship.
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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