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Sram Layout Engineer Jobs (NOW HIRING)

Micron Technology

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

IC layout design experience with NAND, DRAM, and/or SRAM * Programming skills and AI experience relevant to layout workflow Compensation US base salary range: $72.00 - $122.00 per hour. Additional ...

Apple Inc.

SRAM Circuit Design Engineer

Beaverton, OR · On-site

... layout team to create optimal GDS.- Verify extracted GDS meets design specifications.- Backend ... SRAM/Register File for low power, low voltage and high performance. * Knowledge of Cache design ...

Apple Inc.

... layout team to create optimal GDS.- Verify extracted GDS meets design specifications.- Backend ... SRAM/Register File for low power, low voltage and high performance. * Knowledge of Cache design ...

Apple

SRAM Circuit Design Engineer

Austin, TX

$175K - $308K/yr

... with layout team to create optimal GDS. - Verify extracted GDS meets design specifications ... SRAM/Register File for low power, low voltage and high performance. Knowledge of Cache design ...

Apple

SRAM Circuit Design Engineer

Austin, TX

$175K - $308K/yr

... with layout team to create optimal GDS. - Verify extracted GDS meets design specifications ... SRAM/Register File for low power, low voltage and high performance. Knowledge of Cache design ...

Apple

SRAM Circuit Design Engineer

Austin, TX

$175K - $308K/yr

... with layout team to create optimal GDS. - Verify extracted GDS meets design specifications ... SRAM/Register File for low power, low voltage and high performance. Knowledge of Cache design ...

Apple

SRAM Circuit Design Engineer

Austin, TX

$175K - $308K/yr

... with layout team to create optimal GDS. - Verify extracted GDS meets design specifications ... SRAM/Register File for low power, low voltage and high performance. Knowledge of Cache design ...

Qualcomm

Memory Designer

San Diego, CA · On-site

$164K - $246K/yr

Location San Diego, CA Job Area Engineering Group > ASICS Engineering This position involves ... Plan and supervise layout. * Collaborate with the CAD team for full verification and model ...

Micron

Staff Layout Designer - Pathfinding

Boise, ID · On-site

IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and Leveraging Artificial Intelligence (AI) to layout workflow As a world leader in the semiconductor industry, Micron is ...

Micron Technology

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and AI experience relevant to layout workflow The US base salary range that Micron Technology estimates it could pay for ...

Micron

Staff Layout Designer

San Jose, CA

$72 - $122/hr

IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and AI experience relevant to layout workflow The US base salary range that Micron Technology estimates it could pay for ...

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Sram Layout Engineer information

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$45K

$120.8K

$185.5K

How much do sram layout engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for sram layout engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a SRAM layout engineer do?

A SRAM Layout Engineer is responsible for designing and implementing the physical layout of Static Random Access Memory (SRAM) cells and blocks in semiconductor chips. They work closely with circuit designers to translate schematic designs into precise geometric patterns on silicon using specialized CAD tools. Their work ensures that the memory operates correctly, efficiently, and within the required area and power constraints. Additionally, they must consider factors such as manufacturability, yield, and adherence to process design rules.

What are the key skills and qualifications needed to thrive as an SRAM layout engineer, and why are they important?

To thrive as an SRAM Layout Engineer, you need a solid background in semiconductor physics, CMOS circuit design, and VLSI layout methodologies, usually backed by a degree in electrical or electronics engineering. Familiarity with EDA tools like Cadence Virtuoso, layout verification systems (DRC/LVS), and knowledge of industry standards is essential. Attention to detail, problem-solving skills, and effective communication are valuable soft skills for collaborating with design teams and ensuring precision. These skills are crucial for creating efficient, reliable memory layouts that meet performance and manufacturing constraints in advanced integrated circuits.

What are some common challenges faced by SRAM layout engineers during the design process, and how are they typically addressed?

SRAM Layout Engineers often encounter challenges related to optimizing area, power, and performance while ensuring design rule compliance. Balancing tight pitch requirements with manufacturability can be demanding, especially in advanced process nodes. These challenges are typically addressed by closely collaborating with circuit designers, using advanced EDA tools for verification, and participating in regular design reviews to catch potential issues early. Continuous learning and adaptation to new process technologies are also crucial for success in this role.

What is the difference between Sram Layout Engineer vs PCB Design Engineer?

AspectSram Layout EngineerPCB Design Engineer
Primary FocusDesigning SRAM cell layouts and memory arraysDesigning printed circuit boards for electronic devices
Skills & CertificationsVLSI design, CMOS process knowledge, CAD toolsCircuit design, PCB layout, CAD software proficiency
Work EnvironmentSemiconductor companies, chip design labsElectronics manufacturing, product development firms
Industry UsageIntegrated circuit fabricationConsumer electronics, industrial equipment

While both roles involve electronic design, a Sram Layout Engineer specializes in designing SRAM memory cells at the semiconductor level, focusing on transistor layouts within chips. In contrast, a PCB Design Engineer works on creating the physical layout of printed circuit boards for electronic products. Both require strong technical skills and knowledge of electronic design tools, but they operate at different stages of the product development process and within different environments.

What are popular job titles related to Sram Layout Engineer jobs?

For Sram Layout Engineer jobs, the most frequently searched job titles are:

Infographic showing various Sram Layout Engineer job openings in the United States as of September 2026, with employment types broken down into 90% Full Time, and 10% Contract. Highlights an 95% In-person, and 5% Hybrid job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

SRAM/ROM Circuit Design Engineer

Austin, TX • On-site

NXP Semiconductors N.V.
See more jobs at NXP Semiconductors N.V.external

Full-time

Re-posted 2 hours ago

Job description

NXP's Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs.
Our team is part of the Design Enablement/Foundation IP organization within the Chief Technology Office at NXP. We provide differentiating SRAM/ROM memory compiler solutions to NXP SoC design teams across multiple business lines- your work will have real impact for our design teams and, through them, our end products and end customers.
Job Summary:
  • Implement design of CMOS memory circuits to meet memory compiler performance, power, and area requirements, including periphery circuits to support functional safety and scan functionality.
  • Generate, execute, and evaluate simulation characterization measurements and simulation test benches, and compare vs. performance targets/benchmarks.
  • Engage with layout teams on implementation of compiler leaf cells based on designs to improve area and performance.
  • Work closely with CAD teams on implementation of new designs into our characterization, verification, and regression flows.
  • Align with modeling/verification team to ensure consistency of designs with frontend models (behavioral/ATPG/emulation).
  • Collaborate effectively across global memory teams to help ensure common methodologies and best practices.
  • Leverage internally supported LLM/GenAI tools and EDA vendor GenAI solutions to implement efficiencies in design methodologies.

Job Qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline. (Master's degree is preferred).
  • 8+ years of industry experience (6+ with Master's degree) in SRAM memory circuit design, including some design experience with advanced CMOS foundry technologies at 5nm and beyond.
  • Strong familiarity with Cadence Virtuoso and other industry-standard EDA tools.
  • Familiarity with automotive design rules and memory design requirements is a plus.
  • Good knowledge of scripting languages such as Perl, tcl, or Python is a must.
  • Creative mindset, with strong analytical and problem-solving skills.

Job location:
  • The position will be based at the NXP offices in Austin, Texas. Team members are expected to work in office at least 3 days/week.

More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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