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Memory Ic Layout Engineer Jobs (NOW HIRING)

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our ... Contributing to layout tool suites by supporting and/or developing CAD scripts (Memory cell ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

... a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be ... Contributing to layout tool suites by supporting and/or developing CAD scripts (Memory cell ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

... a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be ... Contributing to layout tool suites by supporting and/or developing CAD scripts (Memory cell ...

MediaTek Research Lab Inc.

IC Layout engineer

Irvine, CA · On-site

$85K - $137K/yr

Position Analog Layout Engineer, Analog Design and Circuit Technology, Irvine, California. Responsibilities * Work closely with the design team to develop high‑quality layouts for product ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

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Memory Ic Layout Engineer information

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How much do memory ic layout engineer jobs pay per hour?

As of Sep 10, 2026, the average hourly pay for memory ic layout engineer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What is a Memory IC Layout Engineer?

Memory IC Layout Engineers are specialized professionals who design the physical layout of integrated circuits (ICs) for memory devices like DRAM, SRAM, or Flash. They translate circuit schematics into detailed geometric patterns that define how the various components and interconnections are placed on silicon chips. Their work ensures optimal performance, manufacturability, and reliability of memory devices while meeting strict design rules and minimizing area and power consumption. Memory IC Layout Engineers collaborate closely with circuit designers, verification teams, and fabrication engineers throughout the chip development process.

What are the key skills and qualifications needed to thrive as a Memory IC Layout Engineer?

To thrive as a Memory IC Layout Engineer, you need a solid understanding of semiconductor physics, circuit design, and VLSI layout principles, often supported by a degree in electrical engineering or a related field. Proficiency with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and experience with DRC/LVS verification is essential. Attention to detail, problem-solving ability, and effective teamwork are critical soft skills for excelling in this role. These skills and qualities are vital to produce high-performance, reliable memory ICs while meeting strict design specifications and project timelines.

What are some common challenges faced by Memory IC Layout Engineers, and how can new hires effectively overcome them?

Memory IC Layout Engineers often encounter challenges such as managing tight design schedules, adhering to strict design rules, and optimizing layouts for both performance and manufacturability. New hires can effectively overcome these hurdles by collaborating closely with circuit designers, staying updated on the latest EDA tools, and proactively seeking feedback from experienced team members. Building strong communication skills and being detail-oriented will also help in navigating complex layout requirements and ensuring first-pass silicon success.

What is the difference between Memory Ic Layout Engineer vs Memory Design Engineer?

AspectMemory Ic Layout EngineerMemory Design Engineer
Primary FocusPhysical layout and placement of memory circuits on siliconArchitectural design and performance optimization of memory blocks
Skills RequiredVLSI layout, CAD tools, circuit integrationDigital design, HDL, simulation, architecture
Work EnvironmentFoundries, semiconductor companies, IC design housesDesign firms, semiconductor companies, R&D labs

While both roles involve memory technology, the Memory Ic Layout Engineer focuses on the physical implementation of memory circuits, ensuring optimal placement and manufacturability. In contrast, the Memory Design Engineer concentrates on designing the memory architecture and logic. Both roles require strong technical skills but differ in their core responsibilities within the memory development process.

What are popular job titles related to Memory Ic Layout Engineer jobs?

For Memory Ic Layout Engineer jobs, the most frequently searched job titles are:

Infographic showing various Memory Ic Layout Engineer job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.

IC Layout Engineer III

Princeton, NJ • On-site

SRI International
Scientific Research and Development Services • 1 - 5K employees
Learn more about SRI Internationalexternal

$92K - $122K/yr

Full-time

Posted 29 days ago

Job description

SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC Layout and will be working closely with the SRI Princeton foundry and Design team in the development of form, fit and function emulation (not duplication) of obsolete microcircuits for the U.S. Government.  Target microcircuits are emulated with pre-established gate arrays with only metallization determining the actual circuit function.  The emulated design must meet all specifications and characteristics of the original microcircuit. 


  • Layout of IC designs for existing technologies (CMOS, BiCMOS, Bipolar etc)
  • Generating and/or supervising the creation of IC layout rules (LVS,DRC,ERC) for technologies in development
  • Evaluating layout requirements for designs targeting different technologies (analog or digital)
  • Documenting critical technology information to be used by Layout team
  • Evaluating and enhancing Place & Route algorithms and processes for complex digital designs
  • Contributing to layout tool suites by supporting and/or developing CAD scripts (Memory cell placement, antenna effect mitigation, etc)

  • BS in electrical engineering or related engineering degree, OR 4 years equivalent experience gained through work projects related to design and drafting without a degree.
  • 5 + years of relevant IC layout work experience. 
  • Fundamental knowledge of Integrated Circuit CAD design.
  • Demonstrated analytical and systematic teamwork approach to troubleshooting.
  • Demonstrated ability to effectively communicate with team members (verbal and written).
  • Due to Government requirements candidates must be a US Citizen or Permanent Resident.

The salary range is: $92,160-$122,112. Salary ranges will vary and are based on several factors, including geographic location, market competitiveness and equity amongst internal employees in similar roles. Positions may also qualify for SRI's Pay for Outstanding Performance program or the annual Performance Based Compensation program. SRI also has a competitive benefits package, to view details please go to https://www.sri.com/resources/benefits/. SRI will accept applications until the position is filled.

SRI is an independent nonprofit research institute headquartered in Menlo Park, Calif., with a rich history of supporting government and industry. We create and deliver world-changing solutions for a safer, healthier, and more sustainable future. For almost 80 years, we have collaborated across technical and scientific disciplines to discover and develop groundbreaking products and technologies and bring innovations and ideas to the marketplace.

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