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Memory Ic Layout Engineer Jobs (NOW HIRING)

Final presentation to business leaders Qorvo's IC Layout Engineer Internships are offered in our High Performance Analog business group. Specific projects and responsibilities will be determined ...

Final presentation to business leaders Qorvo's IC Layout Engineer Internships are offered in our High Performance Analog business group. Specific projects and responsibilities will be determined ...

The Layout Design Engineering group is an integral part of the Silicon Engineering department, working closely with the analog RFID end-point IC development team and the Reader IC team ...

The Layout Design Engineering group is an integral part of the Silicon Engineering department, working closely with the analog RFID end-point IC development team and the Reader IC team ...

Associates Degree in Electronic/IC layout CAD specialization or related program and 10+years of IC ... Proactively work with design engineers to achieve efficient circuit performance * Design analog ...

Senior RFIC Layout Engineer

Atlanta, GA

$100K - $138K/yr

Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...

Senior RFIC Layout Engineer

Atlanta, GA · On-site

$100K - $138K/yr

Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...

Senior RFIC Layout Engineer

Atlanta, GA · On-site

$100K - $138K/yr

Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...

Design the memory IC projects from concept to tape-out * Define and implement memory architectures ... Strong understanding of layout design including layout dependent effects, pitch matching, and ...

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Solving layout design issues and applying proactive intervention * Proactively work with design ...

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Memory Ic Layout Engineer information

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How much do memory ic layout engineer jobs pay per hour?

As of Sep 10, 2026, the average hourly pay for memory ic layout engineer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What is a Memory IC Layout Engineer?

Memory IC Layout Engineers are specialized professionals who design the physical layout of integrated circuits (ICs) for memory devices like DRAM, SRAM, or Flash. They translate circuit schematics into detailed geometric patterns that define how the various components and interconnections are placed on silicon chips. Their work ensures optimal performance, manufacturability, and reliability of memory devices while meeting strict design rules and minimizing area and power consumption. Memory IC Layout Engineers collaborate closely with circuit designers, verification teams, and fabrication engineers throughout the chip development process.

What are the key skills and qualifications needed to thrive as a Memory IC Layout Engineer?

To thrive as a Memory IC Layout Engineer, you need a solid understanding of semiconductor physics, circuit design, and VLSI layout principles, often supported by a degree in electrical engineering or a related field. Proficiency with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and experience with DRC/LVS verification is essential. Attention to detail, problem-solving ability, and effective teamwork are critical soft skills for excelling in this role. These skills and qualities are vital to produce high-performance, reliable memory ICs while meeting strict design specifications and project timelines.

What are some common challenges faced by Memory IC Layout Engineers, and how can new hires effectively overcome them?

Memory IC Layout Engineers often encounter challenges such as managing tight design schedules, adhering to strict design rules, and optimizing layouts for both performance and manufacturability. New hires can effectively overcome these hurdles by collaborating closely with circuit designers, staying updated on the latest EDA tools, and proactively seeking feedback from experienced team members. Building strong communication skills and being detail-oriented will also help in navigating complex layout requirements and ensuring first-pass silicon success.

What is the difference between Memory Ic Layout Engineer vs Memory Design Engineer?

AspectMemory Ic Layout EngineerMemory Design Engineer
Primary FocusPhysical layout and placement of memory circuits on siliconArchitectural design and performance optimization of memory blocks
Skills RequiredVLSI layout, CAD tools, circuit integrationDigital design, HDL, simulation, architecture
Work EnvironmentFoundries, semiconductor companies, IC design housesDesign firms, semiconductor companies, R&D labs

While both roles involve memory technology, the Memory Ic Layout Engineer focuses on the physical implementation of memory circuits, ensuring optimal placement and manufacturability. In contrast, the Memory Design Engineer concentrates on designing the memory architecture and logic. Both roles require strong technical skills but differ in their core responsibilities within the memory development process.

What are popular job titles related to Memory Ic Layout Engineer jobs?

For Memory Ic Layout Engineer jobs, the most frequently searched job titles are:

Infographic showing various Memory Ic Layout Engineer job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.

Analog/RF IC Layout Design Engineer.

Santa Clara, CA • On-site

$117K - $195K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 9 days ago


Key responsibilities

  • Lay out full custom BiCMOS, CMOS, and bipolar ICs for test and measurement products.

  • Perform design rule checks (DRC), layout-vs-schematic (LVS), antenna checks, and ensure layout compliance.

  • Collaborate with IC designers to optimize device placement, matching, and layout parameters.


Job description

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

Responsibilities

Keysight Technologies has been and will continue to be the world’s premier measurement company. Keysight Technologies has an opening for an Analog Layout Engineer in its ASIC/MMIC Design Center in Colorado Springs.

This specific position is to support a team of ASIC/MMIC designers by laying out full custom BiCMOS, CMOS, and bipolar (e.g., InP/GaAs) ICs for leading-edge test and measurement products. Through close collaboration with IC designers and experts in IC technologies and IC design tools, you’ll help create breakthrough components for new Keysight products. The position also requires tools and CAD knowledge to develop methodologies and automation to increase productivity and effectiveness.

Job Aspects include:

  • Creating transistor level layout views from schematics, spanning from cell-level up through top-level and full-chip assembly
  • Completing Design Rule Checking (DRC), Layout-vs-Schematic (LVS), Antenna Checks, and maintaining Layout XL compliance
  • Placing device primitives using best practices for thermal and device matching, like common centroid, dummy matching, RF symmetry, interdigitation, etc.
  • Soliciting IC designers for advice and feedback on critical circuit nodes, matching requirements, current density requirements, and other critical parameters for circuit success
  • Knowledge of electro-migration (EMIR) and how to best prevent and correct its effects
  • Understanding of metal density requirements and proper ways to address this type of DRC error
  • Assisting the design team with IC floorplanning, creating grid cells and other custom layouts
  • Coordinating layout activities with other layout engineers and contractors

Complete chip level sign-off verifications

Qualifications

Must have qualifications:

  • BS/MS in Electrical Engineering, or applicable degree and/or relevant experience
  • 7+ years of experience with custom Analog IC Layout experience
  • 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density/slot rules
  • Familiarity with analog design in modern sub-micron BiCMOS (130 nm and smaller)
  • Knowledge of device matching, common centroid practices, parasitic effects, and other techniques for guaranteeing quality results
  • Ability to work on multiple cell designs in parallel in a dynamic environment
  • Experience with Version Control systems (e.g., SVN, Cliosoft/SOS)
  • Excellent teamwork, collaboration, and communication skills as you will work directly with IC design engineers and other layout designers

Additional skills that are nice to have:

  • Basic understanding of simple electrical circuits
  • Experience with Mentor Calibre DRC / LVS and similar EDA tools
  • Layout experience specifically for high-frequency (20+ GHz) bipolar signal path ICs
  • Linux fundamental knowledge
  • SKILL programming or other scripting experience
  • OCEAN experience

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

Careers Privacy Statement

Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.

Most offers will be between the minimum and the midpoint of the Salary Range listed below.

MIN $117,530.00 - MAX $195,880.00

Note: For other locations, pay ranges will vary by region

This role is eligible for Keysight Results Bonus Program

US Employees may be eligible for the following benefits:

  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)
  • Restricted Stock Units

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