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Memory Ic Layout Engineer Jobs (NOW HIRING)

Micron Technology

Layout Engineer, DEG

Boise, ID · On-site

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Our layout engineering team drives the physical design foundations behind Micron ...

Lightmatter

Package Layout Engineer

Mountain View, CA · Hybrid

About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...

Lightmatter

Package Layout Engineer

Mountain View, CA · On-site

$157K - $176K/yr

About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...

Socket.dev

Package Layout Engineer

Mountain View, CA · On-site

$157K - $176K/yr

About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...

Draper

IC Packaging Design & Layout Engineer

Cambridge, MA · On-site

$82K - $220K/yr

The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and reliability ...

Draper

IC Packaging Design & Layout Engineer

Cambridge, MA · On-site

$82K - $220K/yr

The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and reliability ...

Texas Instruments

Analog IC Design Engineer

Dallas, TX · On-site

Direct IC layout to ensure performance, reliability, and manufacturability * Characterize silicon prototypes and develop test specifications in coordination with test and product engineering teams

Texas Instruments

Analog IC Design Engineer

Dallas, TX · On-site

Direct IC layout to ensure performance, reliability, and manufacturability * Characterize silicon prototypes and develop test specifications in coordination with test and product engineering teams

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Memory Ic Layout Engineer information

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How much do memory ic layout engineer jobs pay per hour?

As of Sep 11, 2026, the average hourly pay for memory ic layout engineer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What is a Memory IC Layout Engineer?

Memory IC Layout Engineers are specialized professionals who design the physical layout of integrated circuits (ICs) for memory devices like DRAM, SRAM, or Flash. They translate circuit schematics into detailed geometric patterns that define how the various components and interconnections are placed on silicon chips. Their work ensures optimal performance, manufacturability, and reliability of memory devices while meeting strict design rules and minimizing area and power consumption. Memory IC Layout Engineers collaborate closely with circuit designers, verification teams, and fabrication engineers throughout the chip development process.

What are the key skills and qualifications needed to thrive as a Memory IC Layout Engineer?

To thrive as a Memory IC Layout Engineer, you need a solid understanding of semiconductor physics, circuit design, and VLSI layout principles, often supported by a degree in electrical engineering or a related field. Proficiency with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and experience with DRC/LVS verification is essential. Attention to detail, problem-solving ability, and effective teamwork are critical soft skills for excelling in this role. These skills and qualities are vital to produce high-performance, reliable memory ICs while meeting strict design specifications and project timelines.

What are some common challenges faced by Memory IC Layout Engineers, and how can new hires effectively overcome them?

Memory IC Layout Engineers often encounter challenges such as managing tight design schedules, adhering to strict design rules, and optimizing layouts for both performance and manufacturability. New hires can effectively overcome these hurdles by collaborating closely with circuit designers, staying updated on the latest EDA tools, and proactively seeking feedback from experienced team members. Building strong communication skills and being detail-oriented will also help in navigating complex layout requirements and ensuring first-pass silicon success.

What is the difference between Memory Ic Layout Engineer vs Memory Design Engineer?

AspectMemory Ic Layout EngineerMemory Design Engineer
Primary FocusPhysical layout and placement of memory circuits on siliconArchitectural design and performance optimization of memory blocks
Skills RequiredVLSI layout, CAD tools, circuit integrationDigital design, HDL, simulation, architecture
Work EnvironmentFoundries, semiconductor companies, IC design housesDesign firms, semiconductor companies, R&D labs

While both roles involve memory technology, the Memory Ic Layout Engineer focuses on the physical implementation of memory circuits, ensuring optimal placement and manufacturability. In contrast, the Memory Design Engineer concentrates on designing the memory architecture and logic. Both roles require strong technical skills but differ in their core responsibilities within the memory development process.

What are popular job titles related to Memory Ic Layout Engineer jobs?

For Memory Ic Layout Engineer jobs, the most frequently searched job titles are:

Infographic showing various Memory Ic Layout Engineer job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.

US_West | Manufacturing & Process Engineer_L3

Santa Clara, CA • On-site

Redolent, Inc.
IT Services • 51 - 200 employees
Learn more about Redolent, Inc.external

Contractor

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Role: Analog Layout Engineer
Location: Santa Clara, CA
JOB DESCRIPTION
MUST HAVE:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm, following best practices from the industry.
Qualifications
• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
• Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
• Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
• Experience with floor planning, block level routing and top-level chip assembly.
• Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
• Demonstrated experience with analog layout for silicon chips in mass production.
• Experience with FinFET process nodes preferred
• Experience working with distributed design teams a plus.
• Knowledge of skill code and layout automation a plus.
• Self-starter with the ability to define and adhere to a schedule.
• Must possess strong written and verbal communication skills.
• 10+ years' experience in high performance analog layout in advanced CMOS process.
• Experience in IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm
• LVS, DRC, ERC
• Knowledge of high-performance analog layout techniques
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
  • Global Grade : C
  • Named Job Posting? (if Yes - needs to be approved by SCSC) : No
  • Remote work possibility : No
  • Global Role Family : 61404 (P) Manufacturing & Process Engineering
  • Global Technical Skills Family : 18611 (F) Product Engineering
  • Local Role Name : Analog Layout Engineer
  • Local Skills : Julie Skidmore
  • Languages Required: : English
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About Redolent

Sourced by ZipRecruiter

Redolent, a dynamic and rapidly expanding company committed to excellence in software solutions, where success is fueled by a combination of technical expertise and efficient management practices. Our solutions create a measurable delta in our clients’ productivity and profitability, contributing to their growth and success.

Industry

It services

Company size

51 - 200 Employees

Headquarters location

San Jose, CA, US

Year founded

2008

Social media

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