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How much do silicon design engineer jobs pay per year?

As of Aug 13, 2026, the average yearly pay for silicon design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What is a silicon design engineer?

Silicon Design Engineers are professionals who design and develop integrated circuits (ICs) and semiconductor devices, commonly known as 'chips.' They use specialized software tools to create, simulate, and verify the layouts and functionalities of these microchips, which are essential components in electronic devices. Their work ensures that chips are efficient, reliable, and meet the performance requirements for products such as smartphones, computers, and automotive systems. Silicon Design Engineers often collaborate with hardware and software teams to deliver innovative semiconductor solutions.

What are some common challenges faced by silicon design engineers in the development cycle?

Silicon Design Engineers often encounter challenges such as meeting tight deadlines while ensuring design accuracy and managing complex verification processes. Navigating frequent changes in project specifications and collaborating across cross-functional teams—including software, hardware, and verification—can add layers of complexity. Additionally, balancing power, performance, and area (PPA) trade-offs requires careful analysis and iterative optimization throughout the design cycle.

What are the key skills and qualifications needed to thrive as a silicon design engineer?

To thrive as a Silicon Design Engineer, you need a strong background in electrical engineering, digital logic design, and semiconductor fundamentals, typically supported by a relevant degree. Proficiency with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and knowledge of ASIC or FPGA design flows is essential. Attention to detail, problem-solving abilities, and effective teamwork are key soft skills that set top performers apart. These skills and qualities are crucial for ensuring reliable silicon designs, meeting project requirements, and collaborating efficiently in complex engineering environments.
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Silicon Design Engineer jobs near you
Infographic showing various Silicon Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% Internship, 88% Full Time, 6% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Silicon Design Engineer

Advanced Micro Devices, Inc

San Jose, CA • On-site

$145K/yr

Full-time

Re-posted 3 days ago

Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

27th of 157 rated electronics manufacturers

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.
THE ROLE:
We are seeking a highly motivated Silicon Design Engineer. In this role, you will lead and contribute to the design, integration, verification, and characterization of advanced silicon testchips supporting FPGA and ASIC products on leading-edge process technologies
THE PERSON:
The ideal candidate is a hands-on silicon design engineer with experience across RTL-to-GDS implementation, design verification, and post-silicon validation. You should be comfortable working independently, driving technical challenges to closure, collaborating across teams, delivering successful tapeouts, and communicating effectively in fast-paced environments with a passion for innovation.
KEY RESPONSIBILITIES:
  • Drive the timing-aware/physical-aware synthesis flow using industry-standard tools (e.g., Design Compiler) to generate optimized netlists.
  • Lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, signal integrity optimization, physical verification, and design signoff.
  • Close SoC timing with Static Timing Analysis (STA) using tools such as PrimeTime to validate setup/hold margins across process, voltage, and temperature (PVT) corners.
  • Drive tapeout readiness by performing physical signoff analyses including IR drop, electromigration (EM), noise, DRC/LVS verification, and cross-functional reviews with RTL, DFT, package, and foundry teams.
  • Develop verification plans and testbenches to validate chip functionality, and generate test patterns for post-silicon validation
  • Assist with post-silicon bring-up, debugging, and lab-based validation activities.

PREFERRED EXPERIENCE:
  • Good understanding of CMOS circuit design fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms.
  • Proven experience delivering silicon across advanced process technologies, including FinFET (7nm/5nm/3nm) and emerging Gate-All-Around (GAA) nodes.
  • Expertise in digital ASIC/SoC implementation flows, including synthesis, floorplanning, power planning, placement, CTS, routing, timing closure, and physical signoff using industry-standard tools (Cadence Genus/Innovus and/or Synopsys Fusion Compiler).
  • Strong understanding of CMOS circuit design fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms.
  • Proven experience delivering silicon across advanced process technologies, including FinFET (7nm/5nm/3nm) and emerging Gate-All-Around (GAA) nodes.
  • Hands-on experience with physical signoff methodologies, including STA, IR drop, electromigration (EM), DRC/LVS, noise analysis, and tapeout qualification.
  • Strong analytical and problem-solving skills, with experience debugging complex design implementation issues and driving cross-functional closure.
  • Experience with silicon bring-up, post-silicon validation, and laboratory test equipment is a plus.
  • Proficiency in Python, Tcl, and shell scripting for automation, flow development, and productivity enhancement.

ACADEMIC CREDENTIALS:
Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree and relevant industry experience is acceptable.
This role is not eligible for visa sponsorship.
#LI-DR2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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