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Sign Design Jobs in California (NOW HIRING)

Astera Labs

Physical Design/CAD Engineer

San Jose, CA

$160K - $195K/yr

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning ... Master's preferred. * 2-10 years of experience in PnR and sign-off for complex SoCs in Server ...

Broadcom

Design Engineer

San Jose, CA

$143K - $230K/yr

... Sign-In before you apply. In this position you will use your physical design expertise to do ... physical implementation of challenging designs in 2nm/3nm/5nm technology nodes.The person should ...

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off ...

Broadcom, Inc.

Design Engineer

San Jose, CA · On-site

$143K - $230K/yr

... Sign-In before you apply. In this position you will use your physical design expertise to do ... physical implementation of challenging designs in 2nm/3nm/5nm technology nodes . The person should ...

Astera Labs

Physical Design/CAD Engineer

San Jose, CA · On-site

$160K - $195K/yr

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning ... Master's preferred. * 2-10 years of experience in PnR and sign-off for complex SoCs in Server ...

Google

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Experience in sign-off convergence including STA, electrical checks, and physical verification. * Experience in utilizing AI techniques for faster and optimal Physical Design Convergence (e.g ...

LPA Design Studios

Civil Design Engineer

Irvine, CA · On-site

$66K - $97K/yr

Our "No Excuses" integrated design approach was recognized by the AIA as "a trailblazer in ... In the absence of a signed contract, LPA will not agree to pay any recruiter fee. In the situation ...

Apple

System Design Engineer

San Francisco, CA · On-site

$117K - $161K/yr

... and sign-off. Bachelor's degree. 4+ years experience in physical design of multi-layer boards (MLBs).Experience in circuit design, schematic capture, and system integration.Strong physical ...

Broadcom, Inc.

Package Design Engineer

San Jose, CA · On-site

$141K - $226K/yr

... Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you ... Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages ...

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Sign Design information

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$16

$24

$29

How much do sign design jobs pay per hour?

As of Jun 10, 2026, the average hourly pay for sign design in California is $24.09, according to ZipRecruiter salary data. Most workers in this role earn between $20.87 and $27.07 per hour, depending on experience, location, and employer.

What is the difference between Sign Design vs Sign Fabrication?

AspectSign DesignSign Fabrication
Primary FocusCreating visual concepts and layouts for signsConstructing and assembling signs based on designs
Required SkillsGraphic design, creativity, software proficiencyManufacturing skills, material knowledge, craftsmanship
Work EnvironmentDesign studios, offices, client meetingsWorkshops, manufacturing facilities, on-site installations
Common CertificationsGraphic design certifications, CAD skillsTrade certifications, safety training

Sign Design involves creating the visual concepts for signs, focusing on aesthetics and layout, while Sign Fabrication is about physically building and installing the signs. Both roles often collaborate but require different skill sets and work environments.

What is sign design?

Sign design is the process of creating visual graphics and layouts for signs used in public spaces, businesses, events, and more. It involves choosing appropriate colors, fonts, materials, and images to effectively communicate messages and attract attention. Sign designers consider factors such as visibility, readability, branding, and compliance with regulations. Their work ranges from designing storefront signage to wayfinding systems in large complexes. Good sign design helps ensure that information is conveyed clearly and professionally.

What are some common challenges faced by professionals in sign design, and how can applicants prepare for them?

Sign design professionals often encounter challenges such as balancing creative vision with strict regulatory requirements, meeting tight deadlines, and collaborating closely with clients, fabricators, and local authorities. To prepare for these challenges, applicants should familiarize themselves with zoning and signage regulations, develop strong communication skills, and build proficiency in design software like Adobe Illustrator or CorelDRAW. Being adaptable and detail-oriented is key, as projects frequently require revisions and coordination among multiple stakeholders to ensure the final product meets both functional and aesthetic standards.

What are the key skills and qualifications needed to thrive as a Sign Designer, and why are they important?

To thrive as a Sign Designer, you need strong graphic design skills, proficiency in typography and color theory, and usually a degree or certification in graphic design or a related field. Expertise in design software like Adobe Illustrator, CorelDRAW, and familiarity with large-format printing and sign fabrication processes are essential. Creativity, attention to detail, and effective client communication are standout soft skills for this role. These abilities ensure that signage is visually appealing, functional, and meets both client and regulatory requirements.
What are popular job titles related to Sign Design jobs in California? For Sign Design jobs in California, the most frequently searched job titles are:
What job categories do people searching Sign Design jobs in California look for? The top searched job categories for Sign Design jobs in California are:
What cities in California are hiring for Sign Design jobs? Cities in California with the most Sign Design job openings:
Sign Design jobs near you
Infographic showing various Sign Design job openings in California as of June 2026, with employment types broken down into 77% Full Time, 21% Part Time, and 2% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $50,103 per year, or $24.1 per hour.
Chip Lead / Physical Design Director

Chip Lead / Physical Design Director

Cadence Design Systems Inc.

San Jose, CA • On-site

$159K - $164K/yr

Full-time

Posted 5 days ago

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are excited to welcome highly talented Physical Design Architects and Chip Leads to join our Cadence Performance Solutions Group (PSG). Working at Cadence means collaborating with some of the industry's brightest minds and driving innovation for the world's most advanced companies. Through Cadence's tools, emulation hardware, and IP products, we have supported a diverse range of customers. Enabling products in data centers, advanced driver-assistance system (ADAS) automotive and physical AI, and cutting-edge artificial intelligence verticals.

As an expert Physical Design Architect, you will engage directly with our leading-edge customers to deliver differentiated RTL-to-GDS services in advanced FinFET nodes. You will lead a talented Physical Design team with the goal of not only meeting but exceeding customers' demanding Performance, Power, Area, and Schedule (PPAS) targets. At Cadence, our customers are at the heart of everything we do, and talented leaders like you are essential to turning this passion into tangible results.

Key Responsibilities
  • Serve as the technical leader for Physical Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS. These critical SoCs are targeted for markets such as data centers, automotive, and artificial intelligence.
  • Work directly with customers throughout engagements, from initiation to final GDS delivery, taking ownership of technical decisions, design trade-offs, and innovative problem solving to achieve customer PPA and schedule requirements.
  • Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria to ensure the best features versus cost trade-offs.
  • Collaborate with internal Cadence teams to deliver technical presentations and promote internal AI initiatives to improve quality and efficiency.
  • Work closely with customer or internal RTL/Synthesis teams to ensure that key metrics are achieved efficiently prior to the physical design execution phase gate.
  • Partner with Cadence tools R&D to enhance tools and methodologies to meet and surpass customer requirements.
  • Document and share best practices and lessons learned from ongoing and completed projects to improve efficiency, success rates, and AI adoption in future programs
Job Requirements
  • Fifteen or more years of industry experience in Physical Design.
  • Bachelor's degree in Computer Science/Engineering, Electrical Engineering, or a related field.
  • Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis (including timing constraints).
  • Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing, and power closure.
  • Demonstrated experience in complete design closure for chip top-level projects.
  • Expertise in PPA optimization, including driving trade-offs between performance, power, and area to meet aggressive design requirements.
  • Experience with advanced nodes at 7nm and below.
  • Proficiency in scripting languages such as Tcl, Perl, or Python is essential.
  • Strong customer-facing communication and problem-solving skills.
  • Personal drive for continuous learning and expanding professional skill sets.
  • Experience in building strong technical relationships with internal stakeholders, including RTL, DFT, CAD, and Library teams.
Preferred Qualifications
  • Master's degree in Computer Science/Engineering, Electrical Engineering, or a related field.
  • Prior experience with IC digital implementation flows and front-end EDA tools, including Synthesis, DFT, and Logical Equivalence Checking.
  • Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, or with similar tools like ICC, ICC2, DC, or Primetime is highly desired.
  • Experience with advanced nodes at 5nm and below.
  • Domain expertise in CPUs, GPUs, AI Engines, Networks on Chip (NoCs), or high-speed interfaces.
  • Experience with 3D IC design is a significant plus.
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