You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You'll supervise designers to deliver the complete design and to support ...
Quick apply
You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You'll supervise designers to deliver the complete design and to support ...
Quick apply
You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You'll supervise designers to deliver the complete design and to support ...
San Jose, CA · On-site
$178K - $331K/yr
SerDes IPSystemsEngineering Director Description: This is a unique opportunityto join the rapidly growingDie-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems. We ...
San Jose, CA · On-site
$178K - $331K/yr
SerDes IPSystemsEngineering Director Description: This is a unique opportunityto join the rapidly growingDie-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems. We ...
Irvine, CA · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
Irvine, CA · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You'll supervise designers to deliver the complete design and to support ...
You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You'll supervise designers to deliver the complete design and to support ...
Campbell, CA · On-site
$55 - $57/hr
SerDes Validation Engineer San Jose, CA 12 + Months $55-57/HR Overview: Validate high-speed transceivers, automate test flows, and correlate silicon results with models. What You'll Do: Create ...
Campbell, CA · On-site
$55 - $57/hr
SerDes Validation Engineer San Jose, CA 12 + Months $55-57/HR Overview: Validate high-speed transceivers, automate test flows, and correlate silicon results with models. What You'll Do: Create ...
Description Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in ...
Description Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
San Francisco, CA · On-site
$286K/yr
This position requires deep expertise in leading-edge SerDes technologies (224G+), modern interconnect protocols, and system-level co-design. Description As the SIPI Architect, you will define and ...
San Francisco, CA · On-site
$286K/yr
This position requires deep expertise in leading-edge SerDes technologies (224G+), modern interconnect protocols, and system-level co-design. Description As the SIPI Architect, you will define and ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
$207K - $230K/yr
Role Overview Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP - the connectivity engine powering rack-scale AI ...
New
$207K - $230K/yr
Role Overview Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP - the connectivity engine powering rack-scale AI ...
New
The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SERDES interfaces for various applications on the products. Characterization ...
The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SERDES interfaces for various applications on the products. Characterization ...
San Francisco, CA · On-site
$286K/yr
This position requires deep expertise in leading-edge SerDes technologies (224G+), modern interconnect protocols, and system-level co-design. Description As the SIPI Architect, you will define and ...
San Francisco, CA · On-site
$286K/yr
This position requires deep expertise in leading-edge SerDes technologies (224G+), modern interconnect protocols, and system-level co-design. Description As the SIPI Architect, you will define and ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of ...
San Jose, CA · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
San Jose, CA · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based ...
Quick apply
As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based ...
Austin, TX · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
Austin, TX · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
Austin, TX · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
Austin, TX · On-site
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
San Jose, CA · On-site
$178K - $331K/yr
SerDes IP Systems Engineering Director Description: This is a unique opportunity to join the rapidly growing Die-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems.
San Jose, CA · On-site
$178K - $331K/yr
SerDes IP Systems Engineering Director Description: This is a unique opportunity to join the rapidly growing Die-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems.
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
$108K - $192K/yr
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC ...
$96K is the 25th percentile. Wages below this are outliers.
$80.5K - $99.6K
31% of jobs
$99.6K - $118.7K
5% of jobs
The median wage is $132.5K / yr.
$118.7K - $137.8K
19% of jobs
$152.5K is the 75th percentile. Wages above this are outliers.
$137.8K - $156.9K
26% of jobs
$156.9K - $176K
13% of jobs
$176K - $195K
4% of jobs
$195K - $214.1K
0% of jobs
$214.1K - $233.2K
0% of jobs
$233.2K - $252.3K
0% of jobs
$252.3K - $271.4K
1% of jobs
$271.4K - $290.5K
1% of jobs
$80.5K
$141.4K
$290.5K
| Aspect | Serdes | Network Engineer |
|---|---|---|
| Required Credentials | Typically certifications in electronics, FPGA, or hardware design | Networking certifications like CCNA, CCNP, or CompTIA Network+ |
| Work Environment | Hardware labs, manufacturing facilities, R&D centers | Office settings, data centers, client sites |
| Industry Usage | Telecommunications, data communications, hardware manufacturing | IT, telecommunications, enterprise networks |
Serdes (Serializer/Deserializer) specialists focus on hardware design and signal integrity in communication systems, while Network Engineers manage network infrastructure and connectivity. Both roles require technical expertise but differ in their focus areas and work environments. Understanding these differences helps in choosing the right career path or job search focus.
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Posted 12 days ago
6.7
Based on 49 frontline employees who took The Breakroom Quiz
111th of 141 rated electronics manufacturers
Please Note:
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World's Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.
Samsung Semiconductor Inc. (SSI) is advancing the world's technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.
We power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more with our technology solutions. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.
We believe that innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.
Advanced Circuit and Systems (ACAS) is looking for a Senior Manager, Serdes Analog Design. In this role, you will actively work on architecture and circuits of high-speed interconnect transceiver (Serdes). You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You'll supervise designers to deliver the complete design and to support silicon validation and debugging.
You'll work with a team to develop high-performance and low-power serdes, including display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet using cutting-edge process technologies.
Location: Onsite at our San Jose office 5 days a week
What You'll Do
What You Bring
#LI-VL1
What We Offer
The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.
This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.
Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.
Equal Opportunity Employment Policy
Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
Our Commitment to Innovation and Fairness
At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.
Recruiting Agency Policy
We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.
Applicant AI Use Policy
At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.
Trade Secret Notice
By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.
Applicant Privacy Policy
https://semiconductor.samsung.com/about-us/careers/us/privacy/
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