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Senior Physical Verification Engineer Jobs (NOW HIRING)

Lightmatter

Staff Physical Design Engineer

Mountain View, CA · On-site

$160K - $165K/yr

We are seeking a highly skilled Senior Physical Design Engineer to work on the implementation of ... Implement digital blocks in advanced tech nodes from synthesis through physical verification, using ...

Lightmatter

Staff Physical Design Engineer

Boston, MA · On-site

$147K - $152K/yr

We are seeking a highly skilled Senior Physical Design Engineer to work on the implementation of ... Implement digital blocks in advanced tech nodes from synthesis through physical verification, using ...

Microsoft

Senior Physical Design Engineer

Raleigh, NC · On-site

$160K - $261K/yr

We are looking for a Senior Physical Design Engineer with a dedicated passion for customer focused ... Physical Verification * Formal Equivalency * Power optimization and efficiency analysis * IR-drop ...

Lumilens

Sr. Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Role Overview We are seeking a Senior Physical Design Engineer to join our silicon design team ... verification teams to solve complex implementation challenges unique to advanced-node and high ...

Cypress HCM

Senior Verification Engineer

Suwanee, GA · Hybrid

$150K - $225K/yr

Senior Verification Engineer Also open to staff, principal, or senior principal level engineers! Location: Suwanee, GA 30024 | Relocation assistance provided in form of a sign-on bonus Hybrid Remote ...

Liquid Robotics

Senior Verification Engineer

Jessup, MD · On-site

$104K - $144K/yr

Senior Verification Engineer Liquid Robotics is seeking a Senior Verification Engineer to own test ... age, physical or mental disability, genetic factors, military/veteran status or other ...

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Senior Physical Verification Engineer information

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$126.6K

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How much do senior physical verification engineer jobs pay per year?

As of Jul 22, 2026, the average yearly pay for senior physical verification engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

Are verification engineers in demand?

Verification engineers, including senior physical verification engineers, are in high demand due to the increasing complexity of integrated circuits and the need for thorough design validation. Skills in hardware description languages, EDA tools, and industry standards enhance employability in this field.

What engineers make $300,000 a year?

Senior Physical Verification Engineers in semiconductor design and verification can earn $300,000 or more annually, especially with extensive experience, specialized skills in EDA tools, and working in high-demand markets. Compensation varies based on location, company size, and industry, with senior roles often including bonuses and stock options.

What is the salary of senior SoC verification engineer?

The salary of a senior SoC verification engineer typically ranges from $100,000 to $150,000 annually, depending on experience, location, and company size. Compensation may also include bonuses, stock options, and benefits, with expertise in hardware description languages and verification tools influencing pay levels.

What engineers make $500,000 a year?

Senior Physical Verification Engineers in semiconductor design and verification can reach or exceed a $500,000 annual salary, especially with extensive experience, specialized skills in EDA tools, and working in high-demand markets. Compensation varies based on location, company size, and individual expertise, with top-tier engineers often earning this level through bonuses and stock options.
What cities are hiring for Senior Physical Verification Engineer jobs? Cities with the most Senior Physical Verification Engineer job openings:
What are the most commonly searched types of Physical Verification Engineer jobs? The most popular types of Physical Verification Engineer jobs are:
What states have the most Senior Physical Verification Engineer jobs? States with the most job openings for Senior Physical Verification Engineer jobs include:
Senior Physical Verification Engineer jobs near you
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX

Sunnyvale, CA • On-site

$175K - $280K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 21 days ago

SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 146 frontline employees who took The Breakroom Quiz

8th of 63 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
  • Develop, maintain, and optimize physical verification flows for advanced node SoC's.
  • Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified flow changes
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
  • Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
  • Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
  • Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
  • Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:
  • Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
  • Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
  • Deep expertise in DRC, LVS, PERC and ESD verification methodologies
  • Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
  • Direct foundry DRM experience - able to read, interpret, and implement complex rule decks
  • Experience at advanced nodes (4nm and below)
  • Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
  • Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
    Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to

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