Hillsboro, OR · On-site
$148K/yr
Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...
Hillsboro, OR · On-site
$148K/yr
Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...
Beaverton, OR · On-site
$141K - $145K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT and ...
Beaverton, OR · On-site
$141K - $145K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT and ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
Hillsboro, OR · On-site
$113K - $156K/yr
We are looking for a Senior Physical Design Engineer to join the team. #SCHIE #CSME ... Lawful permanent residents, refugees, and asylees may verify status using other documents, where ...
Hillsboro, OR · On-site
$113K - $156K/yr
We are looking for a Senior Physical Design Engineer to join the team. #SCHIE #CSME ... Lawful permanent residents, refugees, and asylees may verify status using other documents, where ...
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
OR · On-site +1
The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality ...
OR · On-site +1
The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality ...
Beaverton, OR · On-site
$119K - $163K/yr
ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable ... Senior Engineer Design Verification Engineering Job Requisition: 1010.1272.5 / R262669 Job Location:
Beaverton, OR · On-site
$119K - $163K/yr
ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable ... Senior Engineer Design Verification Engineering Job Requisition: 1010.1272.5 / R262669 Job Location:
OR · On-site +1
The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality ...
OR · On-site +1
The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality ...
$119K - $163K/yr
ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable ... Senior Engineer Design Verification Engineering Job Requisition: 1010.1272.5 / R262669 Job Location:
$119K - $163K/yr
ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable ... Senior Engineer Design Verification Engineering Job Requisition: 1010.1272.5 / R262669 Job Location:
Hillsboro, OR · On-site
$122K - $200K/yr
Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features * Document and maintain test plans, driving ...
Hillsboro, OR · On-site
$122K - $200K/yr
Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features * Document and maintain test plans, driving ...
OR · On-site +1
$170K - $250K/yr
The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
OR · On-site +1
$170K - $250K/yr
The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
OR · On-site +1
$170K - $250K/yr
The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable ...
OR · On-site +1
$170K - $250K/yr
The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable ...
NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP verification Team. At NVIDIA, we have crafted a team of outstanding people ...
NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP verification Team. At NVIDIA, we have crafted a team of outstanding people ...
NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team of outstanding people ...
NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team of outstanding people ...
As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional ... Collaborate with architects, RTL developers, and physical design teams to improve verification of ...
As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional ... Collaborate with architects, RTL developers, and physical design teams to improve verification of ...
OR · On-site +1
$104K - $143K/yr
As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will define the verification scope and ensure correctness.
OR · On-site +1
$104K - $143K/yr
As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will define the verification scope and ensure correctness.
OR · On-site +1
$104K - $143K/yr
As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will define the verification scope and ensure correctness.
OR · On-site +1
$104K - $143K/yr
As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will define the verification scope and ensure correctness.
OR · On-site +1
$190K - $285K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
OR · On-site +1
$190K - $285K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
$148K/yr
Full-time
Medical, Retirement, PTO
Re-posted 14 days ago
8.7
Based on 147 frontline employees who took The Breakroom Quiz
18th of 159 rated electronics manufacturers
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.
Key Responsibilities
Physical Verification Support & Issue Resolution
Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations
Technical Content Development & Training
Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies
Verification Methodology Leadership
Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)
Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations
Drive methodology improvements to streamline customer design workflows and enhance verification productivity
Customer Engagement & Technical Excellence
Deliver customer-facing technical support with focus on physical verification challenges and solutions
Support customers through complex verification issues and advanced process technology adoption
Ensure maximum customer satisfaction through expert guidance and responsive technical support
Core Competencies
Self-driven and results-oriented with capability to effectively manage multiple complex tasks
Strong analytical problem-solving skills for complex physical verification challenges
Effective communication skills with experience in collaboration, active listening, and providing constructive feedback
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
3+ years of experience with advanced CMOS processes (22nm and below)
3+ years of combined experience in layout verification and parasitic extraction EDA tools
3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)
Preferred Qualifications
Active US Government Security Clearance with a minimum of Secret level
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)
Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools
Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
Customer facing experience
What We Offer
Opportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applications
Direct customer engagement and technical leadership in advanced semiconductor verification
Access to Intel's most advanced foundry technologies and comprehensive verification tool suites
Competitive compensation
Professional development in physical verification methodologies and foundry services
Direct impact on national security through advanced semiconductor verification solutions
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Manufacturing
10,000+ Employees
Santa Clara, CA, US
1968
