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Senior Design Verification Engineer Jobs in Missouri

Jobtailor

IP Design Verification Engineer

California, MO · On-site

$110 - $170/hr

Closely working with design team to review specifications and architecture, define verification ... Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience ...

Jobtailor

SoC Verification Engineer

California, MO · On-site

$120 - $180/hr

Execute verification plans, including emulation and system simulation models, to ensure design ... Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to ...

ArchKey Solutions

Senior Design Engineer

Fenton, MO · On-site +1

SENIOR DESIGN ENGINEER This position is based out of our Fenton, MO office or fully remote. About ArchKey ArchKey is one of the nation's largest privately held specialty trade installation and ...

Jobtailor

Senior Design Engineer

California, MO · On-site

$100 - $150/hr

Works with Sr. Designer on circuit synthesis from the transistor/resistor level up to the system level, simulation, layout supervision. * Assists ATE development with Design-For-Test methods.

Stellar IT Group

Sr. Systems Engineer

Joplin, MO · On-site

$93K - $127K/yr

Job Title: Sr. Systems Engineer Job Location: Joplin, MO Job Type: FTE ABOUT THE POSITION The ... Skills: design verification,system design,doors,embedded

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Senior Design Verification Engineer information

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$59.1K

$113.9K

$179.6K

How much do senior design verification engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for senior design verification engineer in Missouri is $113,935.00, according to ZipRecruiter salary data. Most workers in this role earn between $89,100.00 and $129,900.00 per year, depending on experience, location, and employer.

What is a senior design verification engineer?

Senior Design Verification Engineers are experienced professionals responsible for ensuring that hardware designs, such as integrated circuits or system-on-chip (SoC) components, meet all functional specifications and quality standards before manufacturing. They create and execute verification plans, develop testbenches, and use simulation tools to identify and resolve design issues. Their expertise helps prevent costly errors, ensuring reliable and functional products. Typically, they collaborate closely with design, validation, and product engineering teams and often mentor junior engineers.

What are the key skills and qualifications needed to thrive as a senior design verification engineer?

A Senior Design Verification Engineer requires deep expertise in digital design principles, verification methodologies (such as UVM or OVM), and a degree in electrical or computer engineering. Familiarity with hardware description languages (like Verilog or VHDL), simulation tools (e.g., Synopsys VCS, Cadence Incisive), and scripting languages (such as Python or TCL) is typically expected. Exceptional problem-solving, attention to detail, and strong communication skills help in collaborating with cross-functional teams and navigating complex verification challenges. These skills and qualifications are vital to ensure robust, high-quality hardware designs that meet performance and reliability standards.

What are some typical challenges faced by senior design verification engineers when working on complex chip designs?

Senior Design Verification Engineers often encounter challenges such as managing verification of increasingly complex and large-scale integrated circuits, ensuring comprehensive coverage, and identifying hard-to-find corner-case bugs. They frequently collaborate across cross-functional teams, including design, firmware, and test engineering, to clarify specifications and resolve issues. Effective communication and a proactive approach to debugging and process improvement are critical, as is keeping up with evolving verification methodologies and tools to ensure high-quality, on-time project delivery.

What is the difference between Senior Design Verification Engineer vs Design Verification Engineer?

AspectSenior Design Verification EngineerDesign Verification Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field; experience in verification tools and methodologiesBachelor's degree in Electrical Engineering, Computer Engineering, or related field; entry-level experience in verification
Work EnvironmentDesign teams, hardware/software verification labs, collaborative projectsVerification teams, testing labs, development environments
Employer & Industry UsageSemiconductor, electronics, hardware development companiesSimilar industries, often as entry or mid-level roles within verification teams

The main difference is experience level and responsibility. Senior Design Verification Engineers typically lead verification efforts, mentor junior staff, and handle complex verification tasks, while Design Verification Engineers focus on executing verification plans and testing designs under supervision. Both roles require similar technical skills and industry knowledge, but the senior role involves more leadership and strategic planning.

What are popular job titles related to Senior Design Verification Engineer jobs in Missouri?

For Senior Design Verification Engineer jobs in Missouri, the most frequently searched job titles are:

What job categories do people searching Senior Design Verification Engineer jobs in Missouri look for?

The top searched job categories for Senior Design Verification Engineer jobs in Missouri are:

What cities in Missouri are hiring for Senior Design Verification Engineer jobs?

Cities in Missouri with the most Senior Design Verification Engineer job openings:

Senior Design Verification Engineer jobs near you
Infographic showing various Senior Design Verification Engineer job openings in Missouri as of June 2026, with employment types broken down into 94% Full Time, 4% Part Time, and 2% Contract. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $113,935 per year, or $54.8 per hour.

IP Design Verification Engineer

Jobtailor

California, MO • On-site

$110 - $170/hr

Other

Posted 17 days ago

Job description

Responsibilities
  • Test bench development
  • Directed/constrained random test generation in UVM
  • Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
  • Run RTL and gate level functional verification, debug failures, and analyze coverage
  • Support mixed‑signal verification using Verilog models of analog IP
Requirements
  • Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
  • IP or SoC verification experience using System Verilog/UVM
  • Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
  • Implementation of verification environments that include use of constrained-random stimulus
  • Code/Functional Coverage analysis
  • Writing System Verilog Assertions (SVA)
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