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Rfic Engineer Jobs in California (NOW HIRING)

SpaceX

EDA Engineer (RFIC Engineering)

Irvine, CA · On-site

EDA ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the ...

SpaceX

EDA Engineer (RFIC Engineering)

Irvine, CA · On-site

EDA ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the ...

SpaceX

EDA Engineer (RFIC Engineering)

Irvine, CA · On-site

EDA ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the ...

3M HEALTHCARE

Senior RFIC Design Engineer

San Jose, CA · On-site

$166 - $229/hr

NXP is seeking a highly motivated and experienced Senior RFIC Design Engineer to contribute to the development of cutting-edge RF integrated circuits for wireless communication systems. Job ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

... engineering. Description As an RFIC Layout Designer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume ...

Apple

RFIC - PLL Design Engineer

Irvine, CA · On-site

$216K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC Design Engineer

Irvine, CA · On-site

Description As a RFIC Design Engineer, you are going to be responsible for providing RFIC solutions for wireless SoC and driving them to mass production for Apple's Wireless Connectivity products.

Apple

RFIC Design Engineer

Irvine, CA

$142K - $263K/yr

As an RFIC Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group, giving to Apple's groundbreaking wireless connectivity solutions into hundreds of ...

Apple

RFIC Design Engineer

Irvine, CA

$142K - $263K/yr

As an RFIC Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group, giving to Apple's groundbreaking wireless connectivity solutions into hundreds of ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in ...

Apple

RFIC Design Engineer

Irvine, CA

$142K - $263K/yr

As an RFIC Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group, giving to Apple's groundbreaking wireless connectivity solutions into hundreds of ...

Apple

RFIC - PLL Design Engineer

Irvine, CA · On-site

$216K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

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Showing results 41-60

All JobsRfic Engineer JobsRfic Engineer Jobs in California

Rfic Engineer information

See California salary details

$32.6K

$88K

$140.1K

How much do rfic engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for rfic engineer in California is $88,015.00, according to ZipRecruiter salary data. Most workers in this role earn between $65,600.00 and $107,600.00 per year, depending on experience, location, and employer.

What is an RFIC engineer?

An RFIC (Radio Frequency Integrated Circuit) Engineer is a professional who designs, develops, and tests integrated circuits that operate at radio frequencies, commonly used in wireless communication devices like smartphones, Wi-Fi routers, and satellites. They work on creating components such as amplifiers, mixers, oscillators, and transceivers that enable high-frequency signal processing on a chip. RFIC Engineers use specialized design tools and simulation software to ensure circuit performance, reliability, and efficiency. Their expertise is crucial in advancing wireless technologies and meeting the demands for faster and more efficient communication systems.

What are the key skills and qualifications needed to thrive as an RFIC engineer?

To thrive as an RFIC Engineer, you need strong expertise in analog and RF circuit design, semiconductor device physics, and typically a degree in electrical engineering or a related field. Proficiency in tools like Cadence, ADS, and EM simulation software, as well as familiarity with industry standards and testing equipment, is essential. Analytical thinking, attention to detail, and effective communication are vital soft skills for successful collaboration and troubleshooting. These skills ensure the development of high-performance, reliable integrated circuits that meet rigorous technical and commercial requirements.

What are some common challenges RFIC engineers face when working on complex chip designs?

RFIC Engineers often encounter challenges such as managing electromagnetic interference, ensuring signal integrity at high frequencies, and meeting stringent power and size constraints in chip designs. Collaborating closely with layout engineers and test teams is essential to address these issues early in the design cycle. Additionally, RFIC Engineers need to stay updated with the latest simulation tools and design methodologies to optimize performance and minimize design iterations.

What is the difference between Rfic Engineer vs RF Engineer?

AspectRfic EngineerRF Engineer
CredentialsBachelor's in Electrical Engineering, RF certificationsBachelor's in Electrical Engineering, RF certifications
Work EnvironmentDesigning and testing RF integrated circuits, working in labs or R&D centersTesting, troubleshooting, and optimizing RF systems in field or lab settings
Industry UsageSemiconductor companies, chip design firmsTelecom, wireless service providers, device manufacturers

Rfic Engineers focus on designing and developing RF integrated circuits, often working in labs or R&D environments. RF Engineers typically handle the deployment, testing, and optimization of RF systems in real-world settings. While both roles require similar credentials and industry knowledge, their primary responsibilities and work environments differ.

What are popular job titles related to Rfic Engineer jobs in California?

For Rfic Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Rfic Engineer jobs in California look for?

The top searched job categories for Rfic Engineer jobs in California are:

What cities in California are hiring for Rfic Engineer jobs?

Cities in California with the most Rfic Engineer job openings:

Rfic Engineer jobs near you
Infographic showing various Rfic Engineer job openings in California as of August 2026, with employment types broken down into 86% Full Time, and 14% Contract. Highlights an 100% In-person job distribution, with an average salary of $88,015 per year, or $42.3 per hour.

EDA Engineer (RFIC Engineering)

SpaceX

Irvine, CA • On-site

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 7 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 149 frontline employees who took The Breakroom Quiz

17th of 72 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
EDA ENGINEER (RFIC ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, hands-on, proactive, and intellectually curious EDA Engineer to help support and improve the IC design environment used by silicon design, layout, verification, physical design, and methodology teams. The role focuses on keeping EDA tools reliable, PDK and flow usage reproducible, and designers productive across analog/RF/mixed-signal and digital silicon workflows.
This is a growth-oriented role for an engineer with strong fundamentals in electrical engineering, computer engineering, computer science, Linux, scripting, or IC design tools. The engineer will partner design teams, other EDA engineers, IT/server teams, foundries, and EDA vendors to triage production issues, improve tool flows, build lightweight automation, maintain documentation, and convert repeated support issues into reusable methodology.
RESPONSIBILITIES:
  • Support day-to-day EDA/CAD workflows for RFIC and silicon engineering teams, including tool launch, environment setup, PDK usage, simulation, physical verification, extraction, and related Linux workflows
  • Support analog/RF/mixed-signal specific flows (Virtuoso, Spectre, EM tools, etc.) in addition to digital and physical verification flows
  • Assist with PDK installation, qualification, version tracking, release notes, and deployment support for supported foundry processes
  • Triage DRC, LVS, PEX, simulation, EM, license, HPC, and environment issues using reproducible debug practices: command, log path, tool version, PDK version, run directory, expected result, actual result, and reproduce status
  • Maintain and improve tool launch wrappers, setup scripts, environment modules, path configuration, project templates, and onboarding material
  • Build lightweight automation in Python, Tcl, SKILL, shell, Perl, Makefile, or similar languages for log collection, preflight checks, license/tool health checks, regression reporting, and recurring issue reduction
  • Create and run targeted QA tests for PDK updates, tool upgrades, wrapper changes, vendor patches, and flow changes before broad deployment
  • Maintain clear runbooks and Confluence documentation for common EDA flows, including DRC/LVS/PEX debug, Cadence/Virtuoso setup, simulation setup, HPC job submission, license issues, and common user errors
  • Partner with design, layout, verification, physical design, IT/HPC, foundry, and EDA vendor teams to resolve blocked flows and improve methodology robustness
  • Identify recurring support patterns and help convert one-off fixes into durable flow changes, documentation, automation, or vendor/IT escalations
  • Support configuration-management and data-management workflows, such as Perforce, Cliosoft, or similar systems, as needed for silicon design teams
  • Contribute to modern EDA workflow improvements, including AI-assisted log triage, rule-deck validation, issue classification, signoff reporting, and designer self-service tools under senior guidance

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering, or computer science
  • 2+ years of experience in EDA/CAD support, IC design flow development, silicon design, physical verification, verification infrastructure, and/or CAD automation

PREFERRED SKILLS AND EXPERIENCE:
  • Master's degree in electrical engineering, computer engineering, computer science, or a related technical field; or equivalent practical experience
  • Hands-on experience using or supporting at least one major EDA flow, such as Cadence Virtuoso/Spectre, Siemens Calibre, Synopsys/Cadence digital tools, Keysight ADS, EMX/HFSS, or similar tools
  • Practical Linux and scripting experience with Python, shell, Tcl, Perl, Makefile, SKILL, or similar languages
  • Ability to independently triage well-scoped user issues, own small flow improvements, document resolutions, and escalate with clear evidence when needed
  • Experience with Cadence Virtuoso, ADE Explorer/Assembler, Spectre, SKILL, design libraries, CDF, techfiles, display resources, or analog/RF/mixed-signal design flows
  • Experience with Siemens Calibre DRC/LVS/PEX/xRC, Synopsys ICV/StarRC, Cadence PegasQuantus, or related physical verification/extraction tools
  • Exposure to PDK installation, PDK QA, foundry design-rule manuals, rule decks, model files, LVS mapping, extraction setup, or PDK release management
  • Exposure to digital design and verification flows such as simulation, regressions, synthesis, STA, power analysis, formal/lint, or regression infrastructure
  • Familiarity with HPC environments, job schedulers such as Slurm or LSF, license servers, FlexNet, Linux modules, wrappers, NFS/storage, and shared compute systems
  • Ability to write clean scripts, parse logs, build sanity checks, and turn repeated errors into automated preflight checks or user-facing runbooks
  • Interest in AI/LLM-assisted EDA workflows, including log triage, runbook retrieval, flow diagnostics, test generation, and signoff report automation

ADDITIONAL REQUIREMENTS:
  • Ability to work long hours and weekends as necessary to support meeting critical milestones

COMPENSATION AND BENEFITS:
Pay Range:
Level 1: $125,000.00 - $150,000.00
Level 2: $145,000.00 - $175,000.00
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
ITAR REQUIREMENTS:
    Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to

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Hours and flexibility

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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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