1

Flip Chip Jobs in California (NOW HIRING)

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump ...

Senior Process Engineer

Carlsbad, CA

$106K - $138K/yr

You will lead process development for flip chip assembly and thermo-compression bonding, support 2.5D and 3D packaging architectures, and play a key role in transitioning processes from development ...

Package Design Engineer

San Jose, CA · On-site

$159K/yr

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part ...

Package Design Engineer

San Jose, CA · On-site

$159K/yr

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.You will be part ...

Package Design Engineer

San Jose, CA · On-site

$141.30 - $226/hr

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part ...

Package Design Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part ...

Package Design Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part ...

next page

Showing results 1-20

Flip Chip information

What is a flip chip?

A Flip Chip job typically involves working with advanced semiconductor packaging technology, where components are flipped and directly bonded to a substrate or circuit board. Responsibilities may include operating equipment, inspecting wafer bonding, troubleshooting defects, and ensuring quality control. Workers in this role are often found in semiconductor manufacturing and may need experience with cleanroom environments, precision tools, and microscopy techniques.

What are the key skills and qualifications needed to thrive in the flip chip position?

To thrive in a Flip Chip process engineering role, you need a strong understanding of semiconductor packaging, microelectronics assembly, and materials science, often supported by a degree in electrical engineering, materials science, or a related field. Experience with tools such as wire bonders, die attachers, flip chip bonders, and knowledge of cleanroom protocols and industry standards like IPC is highly valuable. Attention to detail, problem-solving ability, and excellent teamwork are crucial soft skills for this position. These competencies ensure successful assembly, reliability, and performance of advanced semiconductor devices in a fast-paced and precise manufacturing environment.

What are common challenges faced in a flip chip engineering role?

One of the main challenges in a Flip Chip process engineering position is maintaining high yields and reliability while working with ever-decreasing component sizes and complex assembly processes. Engineers must troubleshoot defects, optimize process parameters, and stay updated with evolving industry technologies. The role often involves cross-functional collaboration with design, quality, and production teams to ensure product integrity. Overcoming these challenges helps build expertise in advanced microelectronic packaging and can position you for advancement within the semiconductor manufacturing industry.

Infographic showing various Flip Chip job openings in California as of August 2026, with employment types broken down into 82% Full Time, 14% Part Time, 3% Contract, and 1% Nights. Highlights an 92% Physical, 3% Hybrid, and 5% Remote job distribution.

Packaging Engineer- Flip Chip

Conductor

San Francisco, CA • On-site

$110 - $170/hr

Other

Posted 6 days ago


Job description

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip).

This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and systemproductization.

Core Responsibilities:

  • Develop and optimize flip chip attach processes including bump formation,

placement, reflow, and underfill for high-performance semiconductor packages.

  • Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps)

and substrate pad finishes for robust interconnect performance.

  • Drive package integration from die to substrate, ensuring alignment, coplanarity,

and yield optimization.

  • Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding,

head-in-pillow, and interconnect defects.

  • Collaborate with substrate vendors, OSATs, and internal teams to define design

rules (pad pitch, bump pitch, keep-outs, stack-ups).

  • Lead process development for reflow profiles, flux selection, cleaning, and underfill

dispense/cure.

  • Perform root cause analysis of assembly and reliability failures using cross-

sectioning, SEM, CSAM, and other failure analysis techniques.

  • Support reliability qualification including thermal cycling, drop, mechanical shock,

and power cycling.

  • Work cross-functionally with design, reliability, thermal, and manufacturing teams

to ensure robust package performance from concept through high-volume

production.

Required Technical Skills:

  • Strong experience in flip chip packaging and assembly processes for

Deep understanding of bumping technologies (solder bumps, Cu pillar, micro-

  • bumps) and UBM/metallization systems.

Experience with underfill materials, dispense techniques, flow behavior, and cure

  • processes.

Understanding of thermo-mechanical behavior in flip chip assemblies (CTE

  • mismatch, warpage, solder fatigue, reliability risks).

Hands-on experience with failure analysis and reliability testing (cross-sections,

  • SEM, CSAM, thermal cycling).

Ability to work with OSATs and suppliers to develop and transfer assembly

  • processes into production.

Strong problem-solving skills with ability to debug yield and reliability issues in

  • manufacturing environments.

Preferred / Differentiating Skills:

  • Experience with III-V packaging, photonics packaging, and precision chip attach.

Experience with advanced packaging technologies including 2.5D interposers, 3D

  • stacking, chiplets, and CoWoS-like architectures.
  • Familiarity with bill of materials used in photonics packaging such as clear

adhesives and underfills as well as mold compounds and underfills for 2.5D

advanced packaging.

  • Familiarity with fine-pitch micro-bump and hybrid bonding approaches.
  • Experience integrating high-power or high-TDP devices with tight warpage and

thermal constraints.

  • Exposure to thermo-mechanical modeling or collaboration with simulation teams

for warpage and reliability prediction.

  • Understanding of system-level interactions (PCB attach, second-level interconnect

reliability).

#J-18808-Ljbffr