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Remote Asic Design Engineer Jobs (NOW HIRING)

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...

Tensordyne

Principal ASIC Architect

Sunnyvale, CA · On-site +1

Headquartered in Sunnyvale, CA, and Munich, Germany, with remote team members across North America ... Work closely with external engineering partners, ASIC design engineers, ASIC design verification ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CA ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Apex Informatics

ASIC Design Verification Engineer

$139K - $169K/yr

Drive Design Verification to closure using defined verification metrics for test plans, functional ... Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or ...

Meta

ASIC Engineer, Power

Sunnyvale, CA · On-site +1

$146K/yr

Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs * Build and optimize EDA infrastructure ...

Meta

ASIC Engineer, Power

Austin, TX · On-site +1

$146K/yr

Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs * Build and optimize EDA infrastructure ...

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Senior ASIC Emulation Engineer

OR · On-site +1

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$178K/yr

ASIC Engineer, Design Verification Responsibilities: * Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification * Develop ...

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Remote Asic Design Engineer information

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$94K

$150.2K

$202K

How much do remote asic design engineer jobs pay per year?

As of Aug 20, 2026, the average yearly pay for remote asic design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a remote ASIC design engineer?

A Remote ASIC Design Engineer is a professional who designs Application-Specific Integrated Circuits (ASICs) while working remotely, often from home or another location outside of a traditional office. They are responsible for creating and verifying digital or analog circuit designs tailored to specific applications, such as telecommunications, automotive, or consumer electronics. These engineers use specialized hardware description languages (HDLs) like Verilog or VHDL and collaborate with teams using online tools for simulation, synthesis, and verification. Remote ASIC Design Engineers must have strong technical skills and the ability to communicate and coordinate effectively in a virtual work environment.

What are the key skills and qualifications needed to thrive as a remote ASIC design engineer?

To thrive as a Remote ASIC Design Engineer, you need a solid background in digital circuit design, Verilog or VHDL programming, and a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as experience in simulation, synthesis, and verification processes, is typically required. Strong problem-solving skills, effective communication, and the ability to collaborate virtually are standout soft skills for remote success. These competencies ensure efficient design cycles, high-quality deliverables, and seamless teamwork in distributed engineering environments.

What are some common challenges faced by remote ASIC design engineers, and how can they be effectively managed?

Remote ASIC Design Engineers often encounter challenges such as coordinating across multiple time zones, ensuring effective communication with hardware and verification teams, and maintaining access to high-performance computing resources. To overcome these hurdles, it’s essential to use collaborative project management tools, establish clear communication protocols, and schedule regular sync meetings. Additionally, many companies provide secure remote access to lab resources and simulation tools, helping engineers stay productive and connected with their teams.

What is the difference between Remote Asic Design Engineer vs Remote FPGA Design Engineer?

AspectRemote Asic Design EngineerRemote FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experienceBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experience
Work EnvironmentDesigning integrated circuits for manufacturing, often in semiconductor companiesDeveloping programmable logic designs, often in research or product development teams
Industry UsageSemiconductor, consumer electronics, automotiveTelecommunications, aerospace, embedded systems

Both roles require similar educational backgrounds and design experience, but the Remote Asic Design Engineer focuses on creating chips for mass production, while the Remote FPGA Design Engineer works on programmable logic devices. Their work environments and industry applications differ, aligning with their specific design goals.

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Cities with the most Remote Asic Design Engineer job openings:

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Remote Asic Design Engineer jobs near you
Infographic showing various Remote Asic Design Engineer job openings in the United States as of August 2026, with employment types broken down into 80% Full Time, and 20% Contract. Highlights an 100% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

ASIC Engineer - Remote

Purple Hires Inc

Plano, TX • Remote

Contractor

Posted 22 days ago

Job description

Job Description
Key skills for Lead ASIC DFT:
 
please see these key words of in the project description for the profile consideration.
  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “
Experience
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.