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onsemi (Nasdaq: ON) is a global leader in intelligent power and sensing technologies, driving innovation to build a safer, cleaner, and smarter world. With a strong focus on automotive, industrial, and AI data center markets, we are shaping the future of vehicle electrification, sustainable energy, and advanced automation.

The Treo Platform is a highperformance analog and mixedsignal platform built on 65nm BipolarCMOSDMOS (BCD) technology. Supporting voltages from 1-90V and operating temperatures up to 175C, Treo enables scalable SoC solutions for automotive, medical, industrial, and AI datacenter applications. Its modular analog IP is integrated into digitalontop architectures manufactured in onsemi's 300mm East Fishkill, NY fab.

We are seeking a MixedSignal Verification Engineer III to verify analog and mixedsignal IP integrated into digitalontop SoC environments on the Treo platform. This midlevel individual contributor role reports directly to the Analog Design Team Manager. You will own the development and execution of mixedsignal verification solutions, leveraging SystemVerilog and behavioral modeling to ensure power and clock IP meet functional and integration requirements prior to tapeout.

Bachelor's or Master's degree in Electrical Engineering or related field.
Minimum of 6 years of experience in mixedsignal or digital IC verification.
Strong proficiency in SystemVerilog and UVMbased verification.
Handson experience building behavioral models using VerilogA/AMS or SystemVerilog realnumber modeling.
Experience verifying analog IP within digitalontop SoC environments.

Familiarity with power management or clocking architectures (BGs, PLLs, LDOs, DC/DCs).
Experience with coveragedriven verification and assertionbased methodologies.
Exposure to automotive or industrial silicon reliability and safety requirements.
Interest in automation, scripting, or AIassisted verification workflows.

Highquality, reusable mixedsignal verification environments delivered on schedule.
Early and effective identification of functional and integration issues in analog IP.
Reduced verification escapes at SoC and silicon bringup stages.
Demonstrated technical growth and mentoring contribution within the verification team.

Own mixedsignal verification for assigned analog IP blocks using SystemVerilog and UVMbased methodologies.
Develop scalable digitalontop testbenches incorporating behavioral models of analog IP such as PLLs, LDOs, DC/DC converters, and oscillators.
Translate analog specifications into executable verification plans, assertions, coverage, and checkers.
Develop and maintain behavioral models using SystemVerilog realnumber modeling to abstract analog behavior for systemlevel simulation.
Execute regressions, analyze results, and drive debug to root cause across analog, digital, and mixedsignal boundaries.
Verify configuration, calibration, monitoring, and faulthandling interfaces between analog IP and digital logic.
Coordinate with analog designers, digital verification, and system teams to ensure verification completeness and signoff readiness.

Create and refine behavioral and functional models suitable for largescale SoC simulation while preserving key performance characteristics.
Define modeling assumptions, limitations, and validation strategies in collaboration with analog designers.
Contribute to abstraction and cosimulation strategies balancing accuracy, runtime, and reuse.

Use industrystandard digital, mixedsignal, and AMS simulation tools.
Apply coveragedriven verification practices and participate in verification reviews.
Follow established version control, regression, and documentation practices; propose incremental flow improvements.

Operate with moderate independence while mentoring junior verification engineers.
Provide technical input during IP definition and integration reviews from a verification perspective.
Proactively identify verification risks and communicate them clearly to stakeholders.