Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ... Analog Layout Engineer * Local Skills : Julie Skidmore * Languages Required: : English
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ... Analog Layout Engineer * Local Skills : Julie Skidmore * Languages Required: : English
Sr. RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$140K - $205K/yr
Bachelor's degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout design in lieu of a degree * 5+ years of professional experience as an IC ...
Sr. RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$140K - $205K/yr
Bachelor's degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout design in lieu of a degree * 5+ years of professional experience as an IC ...
RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$120K - $150K/yr
Bachelor's degree in electrical or computer engineering or 3+ years of professional experience with integrated circuit layout design in lieu of a degree * 1+ years of professional experience as an IC ...
RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$120K - $150K/yr
Bachelor's degree in electrical or computer engineering or 3+ years of professional experience with integrated circuit layout design in lieu of a degree * 1+ years of professional experience as an IC ...
... to layout matching & symmetry, impedance control, and component selection with attention to ... engineers at product concept to properly define characterization/validation setups and product ...
... to layout matching & symmetry, impedance control, and component selection with attention to ... engineers at product concept to properly define characterization/validation setups and product ...
Sr. RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$140K - $205K/yr
Bachelor's degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout design in lieu of a degree * 5+ years of professional experience as an IC ...
Sr. RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$140K - $205K/yr
Bachelor's degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout design in lieu of a degree * 5+ years of professional experience as an IC ...
... layout matching & symmetry, impedance control, and component selection with attention to bandwidth, noise, linearity, and repeatability Working with cross-functional engineers at product concept to ...
... layout matching & symmetry, impedance control, and component selection with attention to bandwidth, noise, linearity, and repeatability Working with cross-functional engineers at product concept to ...
Principal IC Packaging Engineer
San Diego, CA · On-site
We are seeking a highly motivated Principal IC Packaging Engineer to lead the development of advanced integrated circuit (IC) packaging technologies. This role focuses on spearheading new product ...
Principal IC Packaging Engineer
San Diego, CA · On-site
We are seeking a highly motivated Principal IC Packaging Engineer to lead the development of advanced integrated circuit (IC) packaging technologies. This role focuses on spearheading new product ...
RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$120K - $150K/yr
Bachelor's degree in electrical or computer engineering or 3+ years of professional experience with integrated circuit layout design in lieu of a degree * 1+ years of professional experience as an IC ...
RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$120K - $150K/yr
Bachelor's degree in electrical or computer engineering or 3+ years of professional experience with integrated circuit layout design in lieu of a degree * 1+ years of professional experience as an IC ...
Sr. RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$140K - $205K/yr
Bachelor's degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout design in lieu of a degree * 5+ years of professional experience as an IC ...
Sr. RFIC Layout Designer (Starshield Silicon)
Hawthorne, CA · On-site
$140K - $205K/yr
Bachelor's degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout design in lieu of a degree * 5+ years of professional experience as an IC ...
Package Layout Engineer
Mountain View, CA · Hybrid
About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...
Package Layout Engineer
Mountain View, CA · Hybrid
About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$148K/yr
The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and reliability ...
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$148K/yr
The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and reliability ...
The Role We're looking for a Principal RFIC Design Engineer to join the core design team. You'll ... Conduct full-custom IC layout or direct layout engineers, ensuring DRC/LVS-clean designs at mmWave ...
Quick apply
The Role We're looking for a Principal RFIC Design Engineer to join the core design team. You'll ... Conduct full-custom IC layout or direct layout engineers, ensuring DRC/LVS-clean designs at mmWave ...
Package Layout Engineer
Mountain View, CA · On-site
$157K - $176K/yr
About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...
Package Layout Engineer
Mountain View, CA · On-site
$157K - $176K/yr
About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...
We are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning ... Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ...
We are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning ... Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ...
Package Layout Engineer
Mountain View, CA · On-site
$157K - $176K/yr
About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...
Package Layout Engineer
Mountain View, CA · On-site
$157K - $176K/yr
About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Responsibilities * Deliver IC package substrate layouts for standard and advanced packaging ...
Solving layout design issues and applying proactive intervention * Proactively work with design ... Engineering or related program * Comfortable with multiple IC design CAD tools and foundry PDKs
Solving layout design issues and applying proactive intervention * Proactively work with design ... Engineering or related program * Comfortable with multiple IC design CAD tools and foundry PDKs
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$82K - $220K/yr
Summary The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and ...
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$82K - $220K/yr
Summary The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and ...
We are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning ... Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ...
We are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning ... Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ...
We are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning ... Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ...
We are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning ... Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ...
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$82K - $220K/yr
The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and reliability ...
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$82K - $220K/yr
The IC Packaging Design & Layout Engineer is responsible for the end to end creation of advanced integrated circuit (IC) packaging solutions that meet performance, power, size, and reliability ...
Principal Ic Layout Engineer information
See salary details
$74K - $86.6K
3% of jobs
$86.6K - $99.2K
9% of jobs
$99.2K - $111.8K
9% of jobs
$118.1K is the 25th percentile. Wages below this are outliers.
$111.8K - $124.4K
10% of jobs
$124.4K - $137K
10% of jobs
The median wage is $146.6K / yr.
$137K - $149.5K
14% of jobs
$149.5K - $162.1K
13% of jobs
$169.8K is the 75th percentile. Wages above this are outliers.
$162.1K - $174.7K
15% of jobs
$174.7K - $187.3K
11% of jobs
$187.3K - $199.9K
5% of jobs
$199.9K - $212.5K
3% of jobs
$74K
$147.2K
$212.5K
How much do principal ic layout engineer jobs pay per year?
As of Sep 11, 2026, the average yearly pay for principal ic layout engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.
What cities are hiring for Principal Ic Layout Engineer jobs?
Cities with the most Principal Ic Layout Engineer job openings:
What states have the most Principal Ic Layout Engineer jobs?
States with the most job openings for Principal Ic Layout Engineer jobs include:
What are popular job titles related to Principal Ic Layout Engineer jobs?
For Principal Ic Layout Engineer jobs, the most frequently searched job titles are:
US_West | Manufacturing & Process Engineer_L3
Santa Clara, CA • On-site
Redolent, Inc.
 • IT Services • 51 - 200 employees51 - 200 employees
Contractor
This job post has expired 1 day ago. Applications are no longer accepted.
Job description
Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Role: Analog Layout Engineer
Location: Santa Clara, CA
JOB DESCRIPTION
MUST HAVE:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm, following best practices from the industry.
Qualifications
• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
• Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
• Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
• Experience with floor planning, block level routing and top-level chip assembly.
• Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
• Demonstrated experience with analog layout for silicon chips in mass production.
• Experience with FinFET process nodes preferred
• Experience working with distributed design teams a plus.
• Knowledge of skill code and layout automation a plus.
• Self-starter with the ability to define and adhere to a schedule.
• Must possess strong written and verbal communication skills.
• 10+ years' experience in high performance analog layout in advanced CMOS process.
• Experience in IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm
• LVS, DRC, ERC
• Knowledge of high-performance analog layout techniques
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Role: Analog Layout Engineer
Location: Santa Clara, CA
JOB DESCRIPTION
MUST HAVE:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm, following best practices from the industry.
Qualifications
• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
• Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
• Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
• Experience with floor planning, block level routing and top-level chip assembly.
• Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
• Demonstrated experience with analog layout for silicon chips in mass production.
• Experience with FinFET process nodes preferred
• Experience working with distributed design teams a plus.
• Knowledge of skill code and layout automation a plus.
• Self-starter with the ability to define and adhere to a schedule.
• Must possess strong written and verbal communication skills.
• 10+ years' experience in high performance analog layout in advanced CMOS process.
• Experience in IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm
• LVS, DRC, ERC
• Knowledge of high-performance analog layout techniques
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
- Global Grade : C
- Named Job Posting? (if Yes - needs to be approved by SCSC) : No
- Remote work possibility : No
- Global Role Family : 61404 (P) Manufacturing & Process Engineering
- Global Technical Skills Family : 18611 (F) Product Engineering
- Local Role Name : Analog Layout Engineer
- Local Skills : Julie Skidmore
- Languages Required: : English
About Redolent
Sourced by ZipRecruiter
Redolent, a dynamic and rapidly expanding company committed to excellence in software solutions, where success is fueled by a combination of technical expertise and efficient management practices. Our solutions create a measurable delta in our clients’ productivity and profitability, contributing to their growth and success.
Industry
It services
Company size
51 - 200 Employees
Headquarters location
San Jose, CA, US
Year founded
2008