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Custom Ic Layout Methodology Engineer Jobs (NOW HIRING)

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

... custom ASIC / SOC and electronics development across the Semiconductor, Medical and Defense ... methodologies for RF/Analog/Mixed Signal ICs * 3-5 years experience in Cadence layout (Virtuoso ...

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * Bachelor ...

Impinj

Senior Staff Design Engineer, IC Layout

$158K - $238K/yr

Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC ... Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from ...

Impinj

Senior Staff Design Engineer, IC Layout

Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC ... Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC Layout and ...

SRI International

IC Layout Engineer III

Princeton, NJ

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

Qorvo, Inc.

IC Layout Engineering Intern

Richardson, TX · On-site

$31 - $42/hr

Final presentation to business leaders Qorvo's IC Layout Engineer Internships are offered in our ... Learn and apply foundry PDK design rules and layout methodologies. * Support block level floor ...

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How much do custom ic layout methodology engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for custom ic layout methodology engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

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For Custom Ic Layout Methodology Engineer jobs, the most frequently searched job titles are:

Analog IC Layout Engineer

South San Francisco, CA • On-site

Neuralink
Biotechnology Research and Development • 201 - 500 employees
Learn more about Neuralinkexternal

Full-time

Re-posted 15 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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