1

Pmts Silicon Design Engineer Jobs (NOW HIRING)

During the co-design phase, you will partner with silicon design teams, Business Units, customer ... Collaborate with assembly engineering, internal sites, and OSAT/subcontractor partners to conduct ...

Come join Apple's growing wireless silicon development team. Our wireless SOC organization is ... As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ...

PLL Design Engineer

Sunnyvale, CA · On-site

$237K/yr

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...

PLL Design Engineer

Sunnyvale, CA · On-site

$237K/yr

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...

next page

Showing results 1-20

Pmts Silicon Design Engineer information

See salary details

$10

$49

$78

How much do pmts silicon design engineer jobs pay per hour?

As of Jun 10, 2026, the average hourly pay for pmts silicon design engineer in the United States is $49.97, according to ZipRecruiter salary data. Most workers in this role earn between $40.87 and $57.21 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a PMTS Silicon Design Engineer, and why are they important?

To thrive as a PMTS Silicon Design Engineer, you need deep expertise in digital and/or analog circuit design, semiconductor physics, and a relevant engineering degree (such as Electrical or Computer Engineering). Proficiency with EDA tools like Cadence, Synopsys, or Mentor Graphics, as well as experience with Verilog/VHDL and silicon verification methodologies, is typically required. Strong problem-solving abilities, teamwork, and effective communication help drive complex projects and facilitate collaboration across multidisciplinary teams. These skills and qualities are crucial for delivering innovative, high-performance silicon solutions that meet strict industry standards.

What is a PMTS Silicon Design Engineer?

A PMTS (Principal Member of Technical Staff) Silicon Design Engineer is a senior-level engineer responsible for designing, developing, and verifying integrated circuits (ICs) or silicon chips. They typically lead complex hardware design projects, work on architecture specifications, collaborate with cross-functional teams, and mentor junior engineers. Their role is critical in ensuring that the silicon products meet performance, power, and area requirements while adhering to project timelines and quality standards.

What is the difference between Pmts Silicon Design Engineer vs Pmts ASIC Design Engineer?

AspectPmts Silicon Design EngineerPmts ASIC Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering or related field; experience in silicon chip designBachelor's or Master's in Electrical Engineering or related field; specialized ASIC design experience
Work EnvironmentDesign labs, cleanrooms, collaborative teamsDesign offices, simulation labs, cross-functional teams
Industry UsageSemiconductor companies, hardware firmsSemiconductor, consumer electronics, telecommunications

The main difference is that Pmts Silicon Design Engineers focus on designing and developing silicon chips, while Pmts ASIC Design Engineers specialize in creating custom application-specific integrated circuits. Both roles require similar educational backgrounds and work environments, but ASIC design involves more specialized knowledge in custom chip architecture and verification.

What are some typical challenges faced by PMTS Silicon Design Engineers during the chip development process?

PMTS Silicon Design Engineers often encounter challenges such as managing complex design specifications, meeting tight project deadlines, and ensuring designs are both power- and area-efficient without sacrificing performance. Collaboration with cross-functional teams—including verification, physical design, and firmware engineers—is crucial to resolve issues efficiently. Additionally, adapting to evolving industry standards and integrating new technologies can require continuous learning and flexibility to ensure successful tape-out and product delivery.
More about Pmts Silicon Design Engineer jobs
Infographic showing various Pmts Silicon Design Engineer job openings in the United States as of June 2026, with employment types broken down into 84% Part Time, 4% Temporary, and 12% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $103,934 per year, or $50 per hour.
Senior Package Design Engineer

Senior Package Design Engineer

Micron

Boise, ID • On-site

Full-time

Medical, Dental, Vision, PTO

Posted 6 days ago


Micron Technology rating

8.7

Company rating: 8.7 out of 10

Based on 39 frontline employees who took The Breakroom Quiz

11th of 139 rated electronics manufacturers


Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Global Design, Simulation, and Substrate team at Micron Technology is a world-class group of engineers developing advanced semiconductor packaging solutions for memory products including DRAM and NAND. The team operates globally, collaborating with internal assembly sites, technology development teams, and external OSAT partners to deliver high-performance, reliable, and manufacturable package designs across Micron's product portfolio!


As a Senior Package Design Engineer, you will lead co-design activities that bridge silicon design, package architecture, and product development for advanced DRAM and memory products targeting applications such as Mobile, Automotive, Artificial Intelligence, Edge/Cloud Computing, and Data Center. During the co-design phase, you will partner with silicon design teams, Business Units, customer-facing teams, and package and product architecture teams to define and drive new product concepts from inception through High Volume Manufacturing (HVM). Be part of the team! You will collaborate with global, multi-functional teams - including Package Architecture, Technology Development, simulation, and manufacturing - to deliver scalable, high-performance package solutions that meet electrical, mechanical, thermal, and reliability requirements.

Responsibilities
  • Lead co-design activities by partnering with silicon design teams, Business Units, customers, customer-facing teams, and package and product architecture teams to define new product concepts, optimize die floorplans, interconnection schemes, and package architectures from the earliest stages of chip development.
  • Define and optimize package architectures for DRAM products, including substrate stack-up, die padlog optimization, wire bond and flip chip interconnect schemes, and BEOL/RDL flows for advanced memory packages.
  • Lead package layout activities - including floorplanning, placement, and high-density routing - and generate and maintain design databases, package drawings, wire bond diagrams, interposer drawings, and manufacturing documentation.
  • Partner with electrical and simulation teams to interpret parasitic modeling and validation data, and drive design optimization and material selection decisions; conduct feasibility studies and DFM (Design for Manufacturability) reviews to assess and advance designs for performance, manufacturability, and reliability.
  • Partner with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation analysis and feedback into package architecture definition and design optimization for high-speed memory interfaces.
  • Collaborate with assembly engineering, internal sites, and OSAT/subcontractor partners to conduct package and DFMEA reviews, define and manage Assembly DOEs, and ensure designs meet vendor and HVM specifications.
  • Work with SBT (Substrate) suppliers, OSATs, Technology Development, and Package Architecture teams to define and advance design rules and routing methodologies for next-generation packaging solutions.
  • Support the design group's continuous improvement initiatives, including global design alignment, package design rule system development, competitive analysis, package roadmaps, and IP development.
Minimum Qualifications
  • Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related interdisciplinary field with 5+ years of industry experience in advanced memory substrate design, or Bachelor's degree in a related field with 10+ years of industry experience in advanced memory substrate design.
  • Hands-on proficiency with industry-standard EDA tools such as Cadence Allegro Package Designer+ / Integrity 3D-IC Platform, Siemens/MentorGraphics Xpedition tool suite, or equivalent advanced package design tools.
  • Experience in advanced memory substrate design, including flip chip and wire bond interconnects, BEOL/RDL flows, substrate stack-up, and routing for high-density packages.
  • Demonstrated experience partnering with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation analysis and feedback into package architecture definition and design optimization for high-speed memory interfaces.
  • Experience collaborating with OSAT partners, assembly engineering teams, and multi-functional global organizations to deliver package designs through HVM.
Preferred Qualifications
  • 10+ years of industry experience in semiconductor package design, with a focus on advanced DRAM packaging technologies such as LPDDR, HBM, or GDDR, including experience with TSV-based stacking, micro-bump layout, and Chip Package Interaction (CPI) analysis.
  • Experience leading co-design engagements with silicon design teams, customers, or business units - including die floorplan optimization, interconnection scheme definition, and package architecture trade-off studies for new product concepts.
  • Experience with Assembly DOE definition and management, DFMEA reviews, and process/material development in an HVM environment.
  • Proficiency with mechanical drawing tools such as AutoCAD (Autodesk Mechanical) and experience generating package, interposer, and manufacturing drawings.
  • Familiarity with advanced packaging platforms such as 2.5D/3D-IC, fan-out wafer-level packaging (FOWLP), or System-in-Package (SiP) and their associated design and manufacturing ecosystems.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

To learn about your right to work click here.

To learn more about Micron, please visit micron.com/careers

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.


What Micron Technology employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom